Alibaba Pulls Zhenwu V900 Production to Q1 2027, Claims 3x
Alibaba will mass-produce the Zhenwu V900 AI accelerator in Q1 2027. T-Head claims 3x prior performance with 216 GB memory and 1,200 GB/s interconnect, yet discloses no FLOPS or foundry.
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Alibaba will mass-produce its Zhenwu V900 AI accelerator in the first quarter of 2027, the company said at the Apsara Conference 2026. The chip, designed by Alibaba's chip subsidiary T-Head, moves its mass-production date forward from a previously disclosed third-quarter 2027 target.
The V900 carries 216 GB of GPU memory and 1,200 GB/s of inter-chip bandwidth. Those figures sit above the 144 GB and 800 GB/s reported for the prior M890, and they let T-Head build clusters of more than 1,000 V900 chips that operate as a single system. The M890 topped out at 128-chip supernodes.
What does the performance claim rest on?
Alibaba CEO Eddie Wu called the V900 "the most powerful AI chip in China" and said it delivers "three times the performance of the previous-generation M890." T-Head has not disclosed key details that would let analysts benchmark the claim:
- Process node
- Foundry identity
- Power envelope
- Memory bandwidth
- Absolute compute figure in FLOPS
The absence of a FLOPS number leaves the three-times claim difficult to verify. Delivered throughput on real models usually trails calculated peak figures, so the test will be the workload results once chips ship to customers.
How does the V900 compare with Huawei's Ascend 960PR?
Huawei's Ascend 960PR, due in the third quarter of 2027, is rated for 192 GB of memory, 2.4 TB/s of memory bandwidth, and 2.2 TB/s of scale-up interconnect. The published numbers from each vendor line up this way:
- Memory capacity: V900 216 GB vs Ascend 960PR 192 GB
- Memory bandwidth: V900 not disclosed vs Ascend 960PR 2.4 TB/s
- Inter-chip or scale-up bandwidth: V900 1,200 GB/s vs Ascend 960PR 2.2 TB/s
- Mass-production date: V900 Q1 2027 vs Ascend 960PR Q3 2027
The two parts take different roads to scale. Huawei packs more bandwidth per chip. T-Head scales the V900 across a cluster of more than 1,000 devices, then again to a supernode of up to 500,000 cards.
What sits behind the 500,000-card supernode?
The 500,000-card figure refers to the largest configuration T-Head has described for the V900 platform. Each card functions as a node in a fabric that Alibaba says can train models of 5 to 10 trillion parameters.
T-Head's installed base has grown. The unit had shipped more than 560,000 Zhenwu chips to over 400 external customers as of May. Alibaba now puts that count above 650,000 and plans an annual refresh for the line.
T-Head has already shipped at volume, and it intends to keep refreshing the family year after year.
Where does the model roadmap go?
Qwen 4 is in training now, according to Alibaba. The Qwen 4.5 and Qwen 5 families sit further out on the roadmap and will push parameter counts past the 2.4 trillion Qwen3.8-Max and the 2.8 trillion basis of Moonshot's Kimi K3.
On a recent automated run, Qwen3.8-Max completed 33 iterative cycles over a month and lifted its Artificial Analysis score from 40 to 45. A separate EDA experiment with more than 10,000 tool calls over 60-plus hours produced a 42 percent area reduction without performance loss.
Alibaba is pointing to gains on both sides of the loop, models and silicon, as evidence the pipeline is working.
What constrains the buildout?
Wu said "global shortages in the AI supply chain are currently limiting the speed at which we can scale our compute infrastructure." Alibaba Cloud still targets more than 20 gigawatts of data center capacity by 2032.
For reference, SpaceX operates roughly 1.4 GW of AI compute today and has set a target above 10 GW for 2027. Huawei, meanwhile, has shelved its global Ascend rollout, keeping demand pressure on domestic suppliers like T-Head.
The timing of the V900 reveal is not accidental. The announcement lands ahead of the Washington summit between Chinese President Xi Jinping and President Donald Trump, where AI policy sits on the agenda.
The V900 is months from commercial release. The 5-to-10-trillion-parameter model it promises remains untrained. Capacity targets sit six years out, and the proof points will arrive only when T-Head ships silicon.
Source: Tom's Hardware
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Staff writer covering companies, deals and strategy in Semiconductors, chip manufacturing, hardware, AI compute at Chip Dispatch.
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