Altera's Agilex 2X Wraps Third-Gen HyperFlex in a Network-on-Chip

Altera claims a 1.8x improvement in performance per watt for the third-generation HyperFlex fabric at the heart of its new Agilex 2X FPGA SoC family. The flagship Agilex 27 arrives first, with the low-power, low-cost Agilex 22 serving as the entry point for developers who want to scale upward within the same family.

The numbers matter here because Altera is pitching the Agilex 27 squarely at high-throughput workloads: radar signal analysis, machine learning inference and network data stream processing. A fabric that delivers more work per watt, surrounded by better wiring, is the whole commercial argument.

What ties the chip together?

The answer is the HyperFlow Data Network, a network-on-chip (NOC) that connects the HyperFlex FPGA fabric to every major data-moving component on the die. That includes the memory controllers and the CPU complex. The NOC, not point-to-point wiring, is the structural novelty of this generation.

The CPU complex itself steps up from the prior FPGA SoC generation. It pairs Arm Cortex-A720 and Cortex-A520 cores. Developers who prefer softer options can instantiate Nios V cores in the fabric; Nios V is a configurable RISC-V core with versions that run full operating systems such as Linux or real-time environments such as FreeRTOS.

How fast are the interfaces?

The serial transceivers deliver up to 256 Gb/s of throughput. Hard core interfaces support 1.6 T and 800 G Ethernet, plus PCIe 7.0 and CXL. For a chip aimed at network data streams, those are the figures that will decide design wins against competing SoC FPGAs.

The Agilex 27 also carries the expected high-speed GPIO and crypto support. The more speculative feature is UCIe support. Altera positions it as the basis for future Direct RF solutions that place analog-to-digital and digital-to-analog converters in a chiplet-based implementation. In theory, the same UCIe links would simplify integration of third-party IP or off-chip connections. Theory, of course, is doing some load-bearing work in that sentence; the ecosystem has to materialize first.

What is new in the tooling?

Quartus Prime remains the development suite, including the Visual Designer Studio. The addition is Quartus IQ, an AI Expert Companion that brings agentic AI into the FPGA developer's workflow.

The Companion combines FPGA-specific knowledge with project context to apply Quartus skills and agentic workflow support. Its concrete job is faster timing closure: it prioritizes steps across compilation, timing and verification. Altera reports timing closure improvements of 10x and overall design cycle improvements of 1.5x from the AI support.

Those are vendor figures, measured on the company's own examples rather than independent benchmarks. Even discounted, a 1.5x cycle improvement would compress schedules in a market where time-to-revenue on an FPGA design is often the binding constraint.

Why does this generation matter?

The Agilex 2X family pairs a fabric-level efficiency gain with an architectural shift toward NOC-based data movement and a software stack that leans on AI assistance. The combination addresses the two costs that dominate FPGA development: silicon power and engineering time.

The Agilex 27 leads the rollout, with the Agilex 22 extending the family downward for cost- and power-sensitive designs. Developers can move between the two without leaving the HyperFlex architecture or the Quartus toolchain.

The open question is chiplets. If UCIe-based ADC and DAC chiplets arrive as promised, the Agilex 2X becomes a platform rather than a part. Until then, it is a fast, well-connected FPGA SoC with an unusually helpful compiler.