Hardware and semiconductor stocks compounded at 24% annually from 2020 to 2026 — four times the 6% rate of software — as AI compute demand reversed a two-decade hierarchy in which software commanded the market's premium valuations, according to Bain's Technology Report 2026.

The numbers are stark. Hardware and semiconductor market capitalization now sits at roughly $33.7 trillion, ahead of hyperscalers at $12.8 trillion, software at $5 trillion, AI labs at $2.9 trillion, and tech services at $1 trillion, based on S&P, PitchBook and Bain analysis data as of late May 2026. The software compression has earned its own nickname: the SaaSpocalypse.

An AI infrastructure flywheel drives the reversal. Hyperscaler capital expenditure, venture-backed neo-cloud buildouts, and frontier-model development generate step-change demand for compute, and value is pooling in the bottleneck technologies: high-bandwidth memory (HBM), leading-edge silicon, advanced packaging, optical networking and custom accelerators.

HBM: from commodity to kingmaker

Samsung, SK Hynix and Micron have become critical development partners in the AI data center boom, and HBM revenue tells the story: $4 billion in 2023, an estimated $77 billion in 2026, and a forecast $106 billion in 2027 — a roughly 26-fold increase in four years, according to Bain's analysis with Bank of America and New Street Research data.

The technical reason matters commercially. DRAM-based stacks integrate tightly with a base logic die, so customers can no longer swap HBM suppliers as easily as they swapped commodity DRAM. That codevelopment shifts power toward the memory vendors. The margin consequences are unprecedented for a famously cyclical market: SK Hynix and Micron posted record gross margins of 75% to 85% in each of the past two quarters.

There is a cost elsewhere. The three major DRAM players have concentrated most new capacity on HBM, leaving limited investment for conventional DRAM and NAND. That is worsening shortages and pushing up prices of smartphones and PCs.

Advanced packaging picks up Moore's Law slack

As Moore's Law no longer bends the cost curve as it once did, advanced packaging delivers system-level performance and power gains instead. The segment has become a competitive battleground in its own right: semiconductor packaging gross profit grew from $6.1 billion in 2018 to $12 billion in 2022 and $21.5 billion in 2025, with the 2025 mix dominated by advanced packaging — HBM above all — rather than traditional packaging, according to company reports plus Yole, Gartner, UBS, Bank of America and Morgan Stanley data compiled by Bain.

Mature and emerging packaging technologies let chipmakers integrate heterogeneous dies combining logic, memory and I/O with performance approaching monolithic designs. The winners here, Bain argues, will define the next generation of compute density — with TSMC and HBM vendors capturing much of the new value.

Custom silicon goes mainstream

ASICs are now the fastest-growing segment of data center compute chips. Per TD Cowen's Datacenter Silicon Model from April 2026, combined with Epoch AI and Bain analysis, ASIC shipments grew at a 96% compound annual rate and revenue at 84% from 2021 to 2025, and the report estimates further acceleration to 68% shipment growth and 275% revenue growth from 2025 to 2026. CPU shipments actually shrank, at a -6% CAGR over 2021–2025.

Bain identifies four shifts behind the change. First, grand-scale homogeneous workloads — training, inference and agentic — now run at volumes that amortize a custom design. Each workload favors different silicon: training demands dense compute, large HBM and fast scale-up/scale-out; inference's decode phase rereads model weights and the KV cache from memory for every token, rewarding fast on-chip memory; agentic work accumulates context across multistep actions and favors cheaper places to park it, such as KV cache offloading and memory tiering.

Second, buying became punishing, with merchant GPU gross margins as high as 75%. Third, making got cheaper: TSMC, ASIC design houses and EDA vendors now offer chiplets, advanced packaging, foundry capacity and contract design services, letting buyers field custom parts without a full silicon organization. Fourth, silicon accounts for most of a data center's cost and power consumption, so every efficiency gain compounds.

Broadcom's ASIC unit has grown rapidly on hyperscaler demand, while Groq and Cerebras have carved out defensible niches now beginning to scale. ASICs may soon ship in greater volume than Nvidia's GPUs even if Nvidia keeps the larger revenue share.

Capacity, geopolitics and the supply chain

TSMC intends to build nine phases of new fabs this year, more than double its recent annual rate, while increasing manufacturing capacity of chip-on-wafer-on-substrate and system-on-integrated-chips by 80% — and the company still says it cannot keep up with customer demand. Single-source exposure at the leading edge now carries pricing and supply risks from natural disasters, geopolitical disruption and export controls.

Logic foundries are diversifying geographically: Bain's Foundry Capacity Database (June 2026) shows logic wafer capacity growing from about 4.5 million to about 6 million wafers per month by 2030, with added 2026–2030 capacity concentrated in the US, mainland China and rest-of-world rather than Taiwan. Memory tells the opposite story — capacity grows from about 3.5 million to about 5.2 million wafers per month, but South Korea keeps roughly the same share, per Bain's Memory Fab Database (May 2026).

TSMC has committed $260 billion to fabs in Arizona. Governments, treating leading-edge silicon as strategic infrastructure, will push domestic or allied production through subsidies, export controls and local content rules, the report says, while recent Gulf conflicts underline that fabs and data centers must now price in military disruption and transport choke points.

The strategic conclusion cuts across industries: hardware is no longer procurement's remit but a C-suite question of build, buy or partner, with verticalization likely to deepen — Elon Musk's reported Terafab concept, combining logic, memory and packaging under one roof, is the most extreme version of the bet. If Bain's HBM and ASIC trajectories hold, value creation in silicon will become markedly less concentrated, spreading from Nvidia toward the design houses, packaging players and EDA vendors behind the hyperscalers' chips.