
Cadence Says 30% of Chips in Design Use AI Agents, Launches Maestro With Nvidia
Cadence says 20-30% of chips in development now use AI agents. Its Nvidia-tuned Maestro models cut token use up to 5x versus general foundation models.
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- Grace Kim
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Between 20 and 30 percent of chips under development today are designed with the help of AI agents, according to Cadence Senior VP Paul Cunningham, and that share is growing rapidly.
This week Cadence formalized the trend. The company announced a partnership with Nvidia and launched its Maestro AI model family, fine-tuned on Nvidia's Nemotron models to work with and interpret the results of Cadence's own EDA tools.
Early testing showed what specialization buys. Cadence reported "up to" 30 percent higher output quality and "up to" 5x greater token efficiency from Maestro models compared with general-purpose foundation models.
What has Cadence built so far?
Over the past year, Cadence has rolled out a series of AI Super Agents:
- AuraStack, for advanced packaging and PCB layout
- ChipStack, for SoC design and verification
- InnoStack, for PHY routing
- ViraStack, for analog circuit design
Like Anthropic's Claude Code or OpenAI's Codex, these harnesses orchestrate LLMs to automate design and testing flows by sequencing Cadence's existing EDA, test and verification tools. The mechanism mirrors why AI code assistants spread among software engineers: code either compiles or it does not. Cadence likewise has tests to verify and validate designs work as intended.
Why fine-tune instead of using off-the-shelf models?
The effectiveness of verification depends heavily on how closely training data resembles the inputs and outputs the models receive. Cadence's early agents ran largely on off-the-shelf LLMs, which limited exposure to formats such as RTL.
"It's not the case that these amazingly powerful out-of-the-box foundation models are just going to do everything," Cunningham said. "They're the starting point, and you can still specialize."
Specialization pays twice. Post-trained models on Cadence's tools became both smarter and cheaper to run, the company's figures suggest. Cadence distinguishes these vendor-reported numbers as "up to" claims from early testing rather than audited benchmarks.
How will customers deploy Maestro?
The Maestro platform allows customization based on customer data. Cunningham said this will be offered as a managed service rather than something customers configure themselves.
Deployment options are flexible. Customers can access the models via API, run them in a secure VPC, or run them on premises if they have the necessary hardware.
Where does Nvidia fit?
Cadence is not alone in pushing AI agents to orchestrate HPC workloads. Nvidia has spent years driving HPC and AI toward each other, a natural move given its GPUs serve workloads beyond training and running AI, even if that is what most buyers purchase them for.
The concept of AI-driven labs also anchors the Department of Energy's Genesis Mission, which has produced a flurry of new large Nvidia-based supercomputers. Researchers at Sandia National Labs recently demonstrated AI agents developing and testing new hypotheses in what they called a self-driving lab, though those tests lacked modern agent harnesses and even LLMs.
What comes next?
Given the limited funding afforded public researchers, an AI lab assistant that carries on working long after the engineer has gone home for dinner is an attractive proposition. With Maestro's quality and token-efficiency gains now in customer testing, the competitive question is whether rival EDA vendors can match Cadence's blend of domain-tuned models and agent harnesses before AI-assisted design becomes the default rather than the exception.
Original: theregister.com
More from Grace Kim
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Market editor covering people, launches and day-to-day practice in Semiconductors, chip manufacturing, hardware, AI compute at Chip Dispatch.
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