China’s DUV advance comes with a rising manufacturing bill

By Nathan Brooks

Morgan Stanley expects China’s AI-chip self-sufficiency to rise from 42% in 2025 to 70% by 2030. The bank attributes that forecast to new advanced-node capacity, improving yields and heavy state support, while leaving persistent gaps in EUV, high-bandwidth memory and advanced software.

The forecast concerns domestic supply, not process parity. China can add volume while the EUV gap persists.

How far has China pushed DUV?

Export restrictions have kept ASML’s most advanced EUV lithography systems out of China. The Dutch manufacturer builds them exclusively, using 13.5-nanometer-wavelength light to print intricate features on modern processors. Without those machines, Chinese chipmakers have stretched older 193-nanometer deep-ultraviolet immersion tools through multiple exposures. Some analysts put China’s EUV gap with the West at least five years.

A 2023 teardown of Huawei’s Mate 60 Pro found its Kirin 9000S processor made by SMIC on a second-generation 7nm-class manufacturing process without EUV. Later analysis of Huawei’s Kirin 9030 found SMIC’s DUV-based process closer to the density associated with 5nm manufacturing, though still behind the leading processes used by TSMC and Samsung.

Where does multiple patterning become expensive?

Multiple patterning divides an intricate chip layer into simpler patterns, then repeats exposure and etch steps until they approximate the intended design. It works, but each additional mask increases alignment demands, process variation and the chance of defects.

Chris Mack, co-founder and CTO of Fractilia, cited the early industry view that three exposures on a 193-nanometer immersion tool cost about the same as one EUV exposure. “At three, it was about even,” he said. At four masks, with four 193-nanometer masks replacing one EUV mask, EUV became more cost-effective.

The cost penalty does not stay in the lithography department. Designers can leave more space around features so processors remain manufacturable, but the resulting die is larger. Fewer die fit on each wafer, and wafers cost tens of thousands of dollars.

Mack put the commercial test plainly: manufacturers sell die, not wafers. The relevant calculation is how many die fit on a wafer, how many yield, and how many chips can be sold from it.

What does the efficiency gap show?

A June Morgan Stanley report estimated that Chinese DRAM maker CXMT produced only around one-third as many bits per wafer as Western competitors. The analysts attributed roughly one-third of that shortfall to CXMT’s older process node and described access to lithography as a hard ceiling on Chinese memory development.

Douglas Fuller, a researcher at Copenhagen Business School, said: “For advanced logic chips, in theory there could be other innovations to engineer around EUV, but they are not likely to be very efficient and effective.” Mack also said that labels such as 7nm, 5nm and 3nm have almost no meaning without process measurements.

Reporting suggests SMIC’s N+3 process represents meaningful progress toward 5nm-class manufacturing. Actual measurements show it remains significantly less scaled than established 5nm processes from Samsung and TSMC. That gap limits what DUV can substitute today, but not what it can attempt next.

Can DUV still produce competitive memory?

Micron’s 1-alpha generation of DRAM was developed without EUV. Mack said Micron pushed 193-nanometer lithography farther than other memory makers and produced competitive chips entirely with that tool, while Samsung and Hynix used many layers of EUV.

Morgan Stanley believes CXMT’s planned move to 1-alpha DRAM, intended for HBM3e, is achievable without EUV, citing Micron as evidence. Fuller also reckons that by the end of the decade, advanced packaging will let firms use DUV to produce the latest generations of DRAM. Both are forecasts, not demonstrated production results.

Micron designed its products around the manufacturing technology available rather than trying to reproduce an EUV process on older equipment. Mack said China could probably push much farther if it had the full 193-nanometer immersion ecosystem and optimized designs around multiple patterning. Memory’s repetitive structures also make coordination between chip design and manufacturing easier than for complex phone and computer processors; Mack described memory as the easier production problem.

Micron eventually judged EUV worth using. Its newer 1-gamma DRAM process employs EUV, which Micron says delivers more than 30% greater bit density per wafer than the preceding 1-beta generation. EUV carries its own penalty. Stochastic effects arise from the small number of photons in an exposure, and raising the exposure dose improves pattern control while rapidly increasing cost.

Can capacity close the gap?

Morgan Stanley assumes CXMT remains on its 1-alpha process without EUV, yet expects CXMT’s share of global DRAM bit supply to rise from 14% in 2026 to 16% in 2028 through greenfield capacity. Chinese chipmakers can keep pushing DUV while accepting larger dies, lower yields and longer manufacturing times.

Capacity can narrow commercial gaps without closing process gaps. Mack’s practical verdict is that 3nm or 2nm production is unlikely to be economically viable without EUV, leaving China able to gain output and market share without yet matching the West’s most advanced logic.