D-Wave has demonstrated a two-qubit entangling gate with 99.9 percent fidelity and 500-nanosecond gate time. The result appeared this week in Nature and targets the company's superconducting dual-rail qubit architecture, which D-Wave acquired through its $550 million purchase of Quantum Circuits in early 2026.

What did the Nature paper demonstrate?

The paper details a hardware-based approach that detects errors while preserving the dual-rail error hierarchy. The two-qubit gate ran at 99.9 percent fidelity with a 500-nanosecond gate time. In simulation, the architecture cut the logical error rate by a factor of 10 for each increment of error correction applied. Detecting specific errors in hardware should reduce the physical qubit count needed to form a logical qubit, in turn cutting wiring density, cooling load, and classical post-processing overhead as systems scale toward thousands of qubits.

How does dual-rail error correction work?

D-Wave's dual-rail qubits encode a single microwave photon across two superconducting cavities. The encoding yields zero, one, superposition, and a third state that flags photon loss, giving the qubit built-in error detection that competing architectures require extra circuitry to achieve. Rob Schoelkopf, D-Wave chief scientist and Quantum Circuits co-founder, described the design at the January acquisition announcement.

"The qubit is encoded by a single microwave photon that is shared between two superconducting cavities or resonators," Schoelkopf said. "This gives us the usual abilities of quantum bits – a zero and a one and superpositions – but it also gives us a third state in which we can detect when the photon was lost."

The three-tier error hierarchy governs performance. The most common event is an erasure, in which a qubit leaves its computational state and triggers a flag. Phase flips occur less often. Bit flips are rarest. Hardware erasure detection shortens the path to fault tolerance, D-Wave's scientists wrote.

"Our results present numerous opportunities for operating dual-rail cavity qubits at scale with high performance," D-Wave researchers wrote in the paper.

What is the fault-tolerant roadmap?

D-Wave executives previewed the targets in June, when they also folded Quantum Circuits into the company's product organization and announced an expanded superconducting roadmap. The schedule includes:

• A 49-physical-qubit system in 2027 with a 20-fold reduction in physical error rate
• A 181-physical-qubit system in 2028 with a 2,000-fold reduction
• A 10-logical-qubit machine in 2030 for the first error-corrected algorithms
• A 100-logical-qubit system in 2032 capable of more than one million operations for quantum chemistry and quantum AI workloads

D-Wave frames the 181-qubit machine as the scalable blueprint for fault-tolerant architectures.

What is the commercial picture?

D-Wave already runs a growing annealing business. Bookings for the first half of 2026 reached $35.5 million. That figure rose 1,120 percent from $2.9 million booked in the first half of 2025. The company sells Advantage annealing systems through its Leap cloud service and as on-premises hardware.

The annealing roadmap targets superconducting interconnects for multi-chip scaling, a move the company expects will allow its Advantage3 system to reach 20,000 qubits in 2029 and 100,000 qubits in 2031. A prototype I/O technology would scale chip packaging to 100,000 qubits while adding no more than 20 percent more I/O lines than the 4,500-qubit Advantage2 machine requires.

AT&T expanded its use of D-Wave technology last month after cutting network optimization processing time from approximately one hour to 15 seconds, the carrier said. The deployment marked the most prominent commercial endorsement D-Wave has secured since closing the Quantum Circuits deal.

D-Wave's roadmap now carries the most aggressive fault-tolerant timeline in superconducting quantum computing. The schedule depends on hardware milestones the company has not yet demonstrated beyond the two-qubit gate published this week.