EdgeCortix, the Kanagawa, Japan-based edge AI silicon developer, has launched RAIDEN, a chiplet-based accelerator platform that scales from a single die to a four-die flagship delivering up to 3.36 PFLOPS of FP4 AI compute, 256 GB of memory and 1.54 TB/s of die-to-die bandwidth — and it enters the market with customer design wins already secured.

The company positions the platform against a specific systems problem in physical AI: machines that perceive, reason and act in the real world cannot scale by adding accelerators alone. Compute, memory capacity, memory bandwidth, connectivity and software must scale together as AI models and workloads evolve. RAIDEN, EdgeCortix says, addresses that challenge through one architecture and one software environment spanning the full product line.

"Physical AI will not be won by simply building a faster accelerator. It requires a platform where compute, memory, bandwidth, connectivity and software scale together – and where the hardware deployed today can run the models customers adopt years from now," said Dr. Sakyasingha Dasgupta, founder and CEO of EdgeCortix. "That is what we built RAIDEN to do. One architecture and one software platform scaling from a single die inside an intelligent machine to a four-die flagship for the most demanding Physical AI workloads. Most importantly, customers are already designing around RAIDEN."

Three configurations, one architecture

RAIDEN targets what EdgeCortix calls the "thick edge" — an emerging class of high-performance AI systems deployed outside centralized data centers and closer to machines, sensors and operational environments. Rather than building separate architectures for different performance classes, the platform scales through a modular chiplet approach: single-die X1, two-die X2 and the four-die X4 flagship.

All three configurations share the company's latest DNA-X accelerator architecture and the MERA software stack. Compute, memory capacity, memory bandwidth and inter-die bandwidth scale with the platform, letting customers address different performance, power and deployment requirements without migrating to a different AI architecture or software environment. The common architecture preserves software investment when customers move between RAIDEN configurations.

Detailed specifications and deployment positioning for the X1 and X2 configurations will come in subsequent phases of the RAIDEN launch program; the company has disclosed full figures only for the X4 flagship so far.

The confirmed design wins span next-generation aerospace and defense systems, robotic platforms and high-performance edge AI servers, according to the company.

Scaling beyond the package

For workloads that outgrow a single multi-die package, RAIDEN's high-speed chip-to-chip connectivity provides up to 6.4 Tb/s of scale-out bandwidth, extending the architecture across multiple packages at the system level.

The architecture aims to reduce system-level compromises that EdgeCortix says increasingly constrain advanced physical AI workloads: swapping models and data between internal and external memory, aggressive quantization, partitioning AI and non-AI workloads, and splitting a single physical AI pipeline across multiple discrete computing systems.

Central to the design is the latest generation of the DNA-X architecture, which maintains the runtime-reconfigurable capability of earlier EdgeCortix generations while adding micro-code programmable matrix and vector engines. That extension pushes the silicon beyond standard neural-network inference, supporting perception, reasoning, application processing and control workloads running together within one scalable platform — a requirement for physical AI systems that must do more than run neural networks.

A single MERA software stack provides the common development and deployment environment across the RAIDEN family, so models, tools and software investments carry across configurations.

The commercial logic is straightforward: as multimodal, generative and agentic AI models spread across robotics, aerospace and edge server applications, systems must accommodate larger models, greater context, multiple concurrent workloads and tighter real-time constraints within practical power envelopes. EdgeCortix is betting that a single scalable chiplet platform — rather than a family of discrete parts — is the way to capture that demand, and early customer designs suggest the bet is landing in aerospace, defense and robotics before the full X1 and X2 specifications are even public.