Chip Manufacturing

Emergence AI Takes Neuroformal AI From Fabless Deployments Into the Fab

Emergence AI's neuroformal agents are deployed with fabless chipmakers; IDMs want the work extended into fabs, and packaging MOUs are expected within two to three months.

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Nathan Brooks
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Emergence AI says its neuroformal AI technology is now in active deployments with fabless chip companies, and integrated device manufacturers on its customer list are asking the startup to extend the work from design-side data analysis into the fab itself.

Speaking to EE Times at SEMICON India 2026, co-founder and executive chairman Satya Nitta framed the commercial logic bluntly: chip demand outstrips supply, every fab runs at full capacity, and no additional wafers can be pushed through. "While chip production speed cannot be increased, AI can certainly help achieve greater yields per wafer," Nitta said, adding that the company is also mining manufacturing-generated data to catch early indicators of degradation before a problem affects a large batch of wafers.

The technical approach pairs large language models with symbolic AI — the rules-based methodology that dominated the field before deep learning. Nitta described the division of labor as "algorithms proposing while symbolic AI verifies." The goal is provably correct output for mission-critical applications, since LLMs operate probabilistically. Nitta rejected the framing of direct competition with GPT-class models: LLMs are "necessary but not sufficient" for mission-critical problems.

Emergence AI started at the fabless end of the value chain. Fabless firms control data about the chip itself — functional, parametric and overall yield metrics — but lack visibility into fab operations. The company's analysis attributes a yield deviation to a fab process problem, a design flaw, or a testing issue. Wafer and final test problems are common; Nitta noted that probe cards do not always make perfect contact, forcing retests.

The agents scale pattern recognition beyond human capacity. Nitta cited one case in which an agent identified the same failure pattern — in a ring oscillator block — across 30% of 1,500 products, and recommended a redesign of that block. Domain-specific agents also perform root-cause analysis, using device physics knowledge to separate spurious correlations from genuine causes.

Some fabless customers rank among the industry's largest companies; Nitta declined to name them on the record. Several of these customers are IDMs that operate both fabless businesses and fabs. Work began in the fabless portion, and those IDMs are now requesting the company extend into the fab — though Nitta said fab-related work remains at a very early stage.

The next commercial frontier is advanced packaging. Because many packaging technologies are still under development, the focus shifts from catching process failures to uncovering fundamental root causes. One example is coefficient of thermal expansion (CTE) mismatch, which Nitta called primarily a physics challenge. Agents would run finite-element and multiscale physics simulations to demonstrate, for instance, that a glass substrate and copper exhibit a significant CTE mismatch leading to breakdown during thermal cycling — and that redesigning the via, changing the aspect ratio, or thickening the liner would produce a more mature process window. Emergence AI is negotiating with multiple advanced packaging companies, and Nitta anticipates announcements of memoranda of understanding within two to three months. The company has no active engagements with semiconductor tooling companies.

Leadership changes accompanied the commercialization push. Roughly a month ago, Nitta moved into the executive chairman and chief scientist roles when Ian Eslick became CEO. Eslick founded Silicon Spice, an MIT spinout acquired by Broadcom for $1.2 billion, and later directed technology initiatives at U.S. Bank and SoFi. Nitta now oversees long-term research and partnerships; Eslick drives commercialization and scaling.

In India, the company operates post-tape-out only, with no current chip design engagement — though that could change, since verification ranks among the lengthiest design steps and neuroformal AI can accelerate it. Emergence AI is in talks with several potential Indian customers it could not yet name.

The company plans to expand to 500 engineers and R&D scientists within two years — a faster timeline than the three-to-four-year horizon EE Times previously reported. Talent is the bottleneck, so Emergence AI is cultivating it: this summer it ran a school on Lean, the open-source proof assistant language, for over 150 students under Siddharth Gadgil, chief scientist of Emergence India Labs and professor at the Indian Institute of Science, and Ilya Sergey of the National University of Singapore.

Open source is part of the recruitment strategy. The company released Agent-E, an open-source autonomous web agent, in 2024 and plans a similar approach for portions of the neuroformal AI work and its Lean collaboration with Gadgil's lab. With the fab extension, packaging MOUs and a compressed hiring timeline all in motion, the next two quarters will test whether provably correct AI can move from fabless pilot deployments to a structural yield lever across the manufacturing chain.

Original: indexbox.io

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Nathan Brooks

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Senior reporter covering industry trends and analytics at Chip Dispatch.

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