Google Doubles Down on TPUs: 8tx for Confidential AI, Two-Chip 8i Max

Google announced two new systems in its eighth-generation Tensor Processing Unit line on November 9: TPU 8tx, a confidential-computing machine that pairs its training silicon with AMD server processors, and TPU 8i Max, a package that fuses two inference chips into one. Together with the TPU 8t and TPU 8i unveiled at Google Cloud Next in April, Google has now announced four TPU systems in a single year, which the company calls a first.

Neither system contains a new chip. Both are reconfigurations of silicon Google already builds, and that detail is the story. Google is competing on packaging, networking and software speed rather than on fresh silicon generations.

Amin Vahdat, Google's chief technologist for AI and infrastructure, said TPUs now serve nearly 100 customers, including frontier labs, trading firms, retailers and universities. Google did not name any of them. It also gave no general-availability date, pricing or regions for either new system.

What does TPU 8tx change for regulated customers?

TPU 8tx uses the same silicon as TPU 8t, the training chip, hosted alongside 5th Gen AMD EPYC CPUs. Google built it for governments and regulated enterprises that want to run frontier or proprietary models and agents on sensitive data. Hardware-level protection keeps data and model weights isolated while they are processed.

The mechanism addresses a real gap. Data in use normally has to be decrypted in memory, and confidential computing closes that window. Google pitches the system for inference and small-scale training on one box: customers can fine-tune on private data, distill large models into smaller ones, and train agents with reinforcement learning without moving data between clusters.

The system runs on Boardfly, the low-latency network Google built for TPU 8i. Google claims up to 2x lower latency than TPU 8t with a near-zero performance penalty from the security features, though it published no absolute latency or throughput figures. The takeaway: Google is selling trust to customers who could not otherwise put sensitive data on shared AI infrastructure.

Why put two inference chips in one package?

TPU 8i Max places two TPU 8i chips on a single package, doubling compute, on-chip SRAM and high-bandwidth-memory bandwidth relative to TPU 8i while fitting twice the silicon into the existing rack footprint. Google aims it at workloads where memory is the bottleneck: many agents working across a large codebase, hours of video, and the million-token context windows its Gemini models support.

The April specifications give the baseline. Each TPU 8i carries 288 GB of HBM, 384 MB of SRAM and 8,601 GB/s of HBM bandwidth. Google did not publish absolute figures for the Max package.

System	Announced	Built for	Silicon / host
TPU 8t	April 2026	Large-scale pre-training	216 GB HBM, 128 MB SRAM per chip; 9,600-chip superpods
TPU 8i	April 2026	Low-latency serving and reasoning	288 GB HBM, 384 MB SRAM, 8,601 GB/s HBM bandwidth per chip
TPU 8tx	Nov. 9, 2026	Confidential inference, small-scale training	TPU 8t silicon with 5th Gen AMD EPYC CPU hosts
TPU 8i Max	Nov. 9, 2026	Long-context and multi-agent inference	Two TPU 8i chips in one package

Vahdat described TPUs as modular building blocks within Google's AI Hypercomputer that let the company reconfigure systems quickly. Google said it uses its AlphaChip system and Gemini to speed up chip layout. The April chips themselves have not yet shipped broadly; Google said TPU 8t and TPU 8i would be generally available later in 2026, claiming up to 2x better performance per watt than the previous Ironwood generation.

How is Google attacking Nvidia's software lock-in?

Much of the announcement targets the software lock-in that keeps customers on Nvidia GPUs rather than raw hardware performance. Google open-sourced TorchTPU last month so PyTorch and Hugging Face models run natively on TPUs, with TPU backends for the vLLM and SGLang serving frameworks.

It also previewed a TPU agent suite that plugs into Claude Code, Cursor and Google Antigravity to handle onboarding, bottleneck diagnosis and kernel tuning, and released an open-source XLA Serving Engine that serves models across TPUs, GPUs and CPUs. Google said Cloud Pathways and dynamic slicing are now generally available on Google Kubernetes Engine, claiming up to 5x faster job startup and 4.5x faster fault recovery for dynamic slicing.

The new hardware closes gaps rather than opening a lead. Nvidia already offers confidential computing on its GPUs and has strengthened its inference line through a licensing and acqui-hire deal with Groq. Google is also spending heavily on the data centers that will house its TPUs, including a $17 billion campus in Cheyenne and a $15 billion Malaysian commitment, and last week it backstopped Anthropic's Kentucky lease with TeraWulf.

The competitive question now is execution: whether Google can ship the April chips broadly, price access to the new systems, and convert its software push into workloads that would otherwise default to Nvidia.