IBM will open its 0.7-nanometer nanostack process to external chip designers in the first quarter of 2027, shipping process design kits for a technology the company positions as a candidate for the next breakthrough in reducing AI chip size.

That date matters. It gives the semiconductor industry its first concrete commercial timetable for a nanostack-class process — an architecture that departs from the planar and gate-all-around transistor scaling that dominates today's leading-edge roadmaps.

What is IBM actually offering?

The commitment is specific: qualified designers get access to the 0.7nm nanostack process through design kits, the standard entry point by which foundries and research fabs let external teams build chips on a given node. IBM has not yet disclosed which customers have lined up, what wafer volumes the program supports, or where the process would run in production.

The 0.7nm figure itself signals intent. It sits well beyond the nodes currently in volume manufacturing, and it frames nanostack technology as a post-roadmap contender rather than an incremental step.

Why AI chips anchor the pitch

IBM frames the technology around AI chip size. Accelerators for large models have become the industry's most demanding customers for area, power and interconnect density, and any process that can shrink logic and memory stacks vertically — the essence of a nanostack approach — directly targets the packaging and scaling bottlenecks that constrain today's AI silicon.

The company's claim is directional, not proven: nanostack technology could be the next breakthrough, as IBM's own positioning puts it. No throughput figures, yield data or customer commitments accompany the announcement yet.

What happens between now and Q1 2027

Shipping design kits is the first gate, not the finish line. Designers receiving kits in Q1 2027 would still face the usual arc that follows any new process disclosure: qualification, IP library development, test silicon, and only then volume manufacturing — a cycle that historically stretches years beyond initial kit availability.

The competitive context sharpens the stakes. Leading-edge foundries are racing toward comparable density territory with gate-all-around and backside-power technologies, so IBM's window to prove nanostack manufacturability before alternatives consolidate the market is finite.

For now, the industry has a date and a node name. Whether Q1 2027 turns into working silicon for external customers — or a research里程碑 that slips — will depend on details IBM has yet to publish, starting with who receives the first kits and what the initial design-win pipeline looks like.