By Grace Kim

University of Illinois researchers stacked three single-crystal silicon tiers at bonding temperatures below 200°C. Device yields reached 98 to 100 percent. The findings appeared in Nature on May 30, 2026.

Materials science professor Qing Cao led the work at the Grainger College of Engineering. His group fabricated the layers using silicon nanomembranes 10 nanometers thick or thinner. That compares to the 500 to 700 micrometer thickness of a standard production wafer.

What did the team build?

Three stacked tiers. Each tier carried 625 junctionless transistors. The design eliminates the high-temperature doping step that normally exceeds 600°C in conventional transistor flows.

The junctionless transistors rely on heavily and uniformly doped silicon films applied before the stacking step, which keeps parasitic contact resistance low across every layer in the final three-tier stack.

Current densities matched those of bulk-silicon devices built at high temperature. Output exceeded monolithic devices made from alternative channel materials by a factor of three to four.

The researchers connected the layers with vertical metal interconnects. They demonstrated working 3D logic circuits and 6-transistor SRAM cells, the basic cache memory element in modern CPUs.

Why does temperature matter so much?

Conventional silicon fabrication approaches 1,000 degrees Celsius. That heat would destroy metal interconnects already patterned in lower layers. The industry accepts 400°C as the ceiling for any layer added after the first circuit tier.

Prior attempts used polycrystalline silicon, amorphous metal oxides, carbon nanotubes, or 2D materials as the upper channel material. All showed performance or reliability gaps when paired with the single-crystal silicon transistors underneath, creating a fundamental mismatch in device characteristics that has blocked commercial adoption.

Cao's group formed freestanding nanomembranes on a donor wafer, then laminated them onto a finished substrate using a roll laminator at no more than 200°C. The thin films conform to surface topography and avoid the voids common to rigid wafer bonding.

"For the first time we have met the thermal budget of monolithic 3D integration using standard single-crystalline silicon and delivered unprecedented performance," Cao said.

How does this differ from AMD 3D V-Cache?

Commercial 3D stacks bond finished wafers together after processing. AMD's 3D V-Cache and high-bandwidth memory are the leading examples in volume production today. Their through-silicon vias are large and sparse. Alignment tolerance is coarse compared to monolithic flows.

Monolithic integration builds each new tier directly on the one below at nanometer-scale alignment. It permits interlayer connections 10 to 100 times denser than conventional wafer bonding, according to prior research the Illinois team cites.

Who funded the work?

The Center for Advanced Semiconductor Chips with Accelerated Performance hosted the research. Industry partners included IBM, Intel, and Taiwan Semiconductor Manufacturing Company. Funding came from the National Science Foundation and the Silicon Crossroads Microelectronics Commons Hub. Industry partners of the Center for Advanced Semiconductor Chips with Accelerated Performance also contributed.

What happens next?

Cao said the process is scalable beyond three layers. The team is preparing to transfer the technology to an industrial semiconductor foundry. Adoption in commercial production will hinge on the outcome of those foundry trials, which are scheduled in the coming months.

Cao framed SRAM as the clearest early application. Today, storing a single bit in static RAM requires six transistors on one plane. Vertical integration could spread those devices across multiple tiers instead.

The Nature paper carries DOI 10.1038/s41586-026-10496-6.