Interconnects and AI Constraints Lead Nov. 11 Blog Roundup

Bodewell Group's Dean Freeman, drawing on the recent SEMI Market Symposium, described AI as a force that could take semiconductor revenue from the $1.5 trillion mark toward $3 trillion over the next decade. The endpoint is a forward-looking industry forecast, not booked revenue or committed capacity; the roundup reports no fab investment, process node, wafer size or shipment number.

Synopsys' Charlie Matar finds that interconnects are “becoming more influential components of both the silicon and system architecture.” His mechanism is straightforward: AI infrastructure scales only when data reaches the right processor at the right time and at an acceptable power cost. Faster arithmetic cannot compensate for data that arrives late, goes to the wrong place or consumes too much power.

Technology strategy adviser Geoff Tate reaches a related conclusion, arguing that exponentially increasing AI compute performance requires exponentially higher interconnect speeds. Intel Foundry's Prashanth Aprameyan names power delivery, connectivity, advanced packaging and supply-chain resilience as the primary constraints on AI scaling.

Rambus' Maxim Demchenko says the location of network security functions in AI HPC and data centers is now a critical architectural decision. Siemens EDA's Muhammad Hassan, Mahmoud Mahany and Mohamed Saleh say 3D IC signal-integrity analysis must account for interactions across different interconnects, package transitions and neighboring high-speed channels.

PDF Solutions' John Kibarian calls AI the most consequential shift the semiconductor industry has faced. The practical limit is now system integration, not processor performance alone.

How should engineers verify the system?

Cadence's Pratik Kumar Gupta shows how Adaptive Traffic Profiles help ascertain whether an interconnect will sustain the bandwidth of real traffic. Protocol compliance alone does not establish performance under actual demand, so the method tests the link against traffic conditions.

Siemens' Bhanu Pandey warns that floating nets in analog power-down circuits “represent a hidden reliability risk” that can evade even rigorous conventional verification flows. The issue is a failure mode that standard checks may miss unless the circuit structure is examined directly.

Arm's Emanuele Rocca highlights security features designed to mitigate Control Flow attacks. In those attacks, a successful exploit overwrites the return address of the function currently executing, or the target pointer of an upcoming jump, with an address in memory controlled by the attacker.

Together, these checks target conditions that ordinary compliance or functional testing can miss. The common need is verification tied to real traffic, real circuit states and deliberate control-flow manipulation.

Where do packaging and test become bottlenecks?

Onto Innovation's John Chang outlines how yield prediction can reduce trial and error in advanced packaging lithography. The method shortens learning cycles by using predicted yield information while advanced packaging processes move toward routine production.

Teradyne's Matthew Knowles shows why the design and test ecosystems must align. His point concerns the handoff between engineers who define a product and engineers who determine how it is tested.

Imagination's Mario Florea outlines a reusable optimization approach for engineers building GPU compute kernels. His example turns Conv2D into a practical GPU compute pattern, giving developers a repeatable method for adapting the operation to graphics processing hardware.

Infineon's Maya Chou examines the benefits of a separate bias regulator dedicated to the gate driver. Her focus is high-reliability space GaN designs, where a dedicated regulator gives the gate driver its own bias supply.

Manufacturing gains depend on less trial and error, while test and design decisions must remain aligned. Chang and Knowles therefore point to the same operating need: fewer unknowns and tighter coordination.

What changes in navigation and automated driving?

Keysight's Ricardo Verdeguer Moreno identifies three macro trends shaping the market for position, navigation and timing technologies. His list moves from system resilience to two space-based markets:

• A stronger focus on resilience and anti-spoofing.
• Low Earth orbit services.
• Lunar navigation.

Together, these trends broaden demand from conventional PNT toward resilience, orbital services and navigation on the Moon. They also shift attention toward proof of position and timing under different operating conditions, from spoofing resistance to low Earth orbit and lunar use.

Cadence's Michael Tran examines what is needed to prove that an automated driving system works safely. The evidence must establish safe operation rather than simply show that automated-driving functions can run.

The shared commercial requirement is credible proof under tougher operating conditions. Basic functionality is no longer enough for these safety-sensitive systems.

The Nov. 11 posts portray a semiconductor industry constrained less by isolated chip design than by links among design, packaging, power, test and security. Freeman's path from $1.5 trillion toward $3 trillion therefore depends on solving engineering constraints across that chain, not only increasing compute performance.

AI demand remains the forecast's driving variable. If that demand continues, advances in interconnect bandwidth, shorter packaging yield-learning cycles and stronger verification will determine how quickly the projected $3 trillion becomes realized revenue.