Micron maps 1δ DRAM, wafer bonding and vertical memory

By Tom Whitfield

Micron has scheduled volume production of its 1δ DRAM process for the second half of 2027. The node promises a mid-20% increase in bit density and targets HBM5, vertical high-bandwidth memory and vertical edge inference memory.

The 1δ (delta) process follows 1γ (gamma), which Micron already produces in high-volume manufacturing. It offers a near-term density gain after Micron removed 4F2 cells from its roadmap, while rivals prepare smaller DRAM transistors for the end of the decade.

How will Micron scale DRAM after 1δ?

Micron plans to introduce wafer bonding with 1ε (epsilon), which the company has under development. It has disclosed neither the implementation method nor the expected density or performance gains, so 1ε remains a planned process rather than a defined one.

Beyond 1ε, Micron plans High-NA EUV lithography for ζÅ (zeta angstrom), its first-generation sub-10nm-class DRAM node. For ηÅ (eta angstrom), its second-generation node in that class, Micron also plans new materials to continue shrinking DRAM cells.

For fabrication technologies expected to shape the next five to 10 years, Micron is collaborating with Albany NanoTech. Scott DeBoer, president and chief technology and products officer, said: “Albany NanoTech, our announced focus on advanced lithography [is] really driving High-NA EUV roadmap for DRAM.”

DeBoer said the Albany team is focused on the next five to ten years. Most of this work concerns fundamental, pre-competitive intellectual property that could enter DRAM production at some future point, rather than a defined manufacturing process.

Micron also lists two 3D DRAM generations, 3D1 and 3D2, between ζÅ and ηÅ on its roadmap. It has disclosed neither their architectures nor launch schedules because it wants 3D DRAM to offer sufficient cost, complexity and performance advantages over conventional planar DRAM.

DeBoer described 3D DRAM as a parallel path that Micron will implement according to cost, complexity and device performance. He said: “DRAM is nearing atomic limits at this point.”

Micron nevertheless retains confidence in several more planar nodes and will time 3D DRAM for the best cost and performance. For now, 1δ is the only dated new production step, while wafer bonding, 3D DRAM and High-NA EUV remain roadmap programs.

Why is Micron putting memory above processors?

Micron is developing vertical high-bandwidth memory, or vHBM, and vertical edge inference memory, or vEIM. The company also works on custom high-bandwidth memory implementations, or cHBM. vHBM places memory stacks directly on top of AI accelerators and AI GPUs rather than beside them.

Shorter connections promise substantially lower latency and higher bandwidth. Heat remains a major obstacle, however, and the arrangement limits how many memory stacks Micron can integrate above one ASIC.

Micron expects vHBM to complement conventional HBM rather than replace it. Conventional HBM will continue to provide most memory capacity in many AI accelerators, while vertical stacks target faster local access.

vEIM shares vHBM's architectural and packaging characteristics but serves a different market. It prioritizes energy efficiency for edge AI processors used in autonomous vehicles, robotics and other power-constrained devices, rather than maximum accelerator bandwidth.

Even first-generation vEIM targets 2 TB/s of bandwidth at less than 1 pJ/bit. Micron describes that target as comparable with HBM4, which currently offers 8 GT/s over a 2,048-bit interface.

The company plans to optimize vHBM, vEIM and cHBM with customers for their required bandwidth, capacity and power levels. Micron has disclosed no commercial production dates for any of the three products, so their technical targets are defined while their market timing remains open. In short, vHBM aims at bandwidth, vEIM at efficiency, and conventional HBM retains the capacity lead.

What role will advanced packaging play?

Both vertical architectures require hybrid bonding, which enables much denser connections than conventional microbumps. Thermal management is equally critical, especially for vHBM, where Micron is developing specialized heat-spreading structures to move heat from hot regions of memory base dies through the DRAM stacks.

The commercial effect reaches beyond DRAM density. Future memory performance will depend more heavily on advanced packaging and closer processor integration, requiring DRAM makers and logic developers to collaborate earlier in ASIC design.

That collaboration turns memory from a commodity into a critical ingredient of an ASIC design. It also ties Micron's process work to packaging and thermal development, while commercial dates for the new products remain undisclosed.

As the vertical packages mature, Micron could compete more directly for AI memory capacity, although it has disclosed no launch dates, capacity commitments or pricing. The next firm checkpoint remains the second-half 2027 start of 1δ volume production.