AI & Compute

Microsoft Targets Nvidia Dependence With Maia 300 AI Chip

Microsoft has begun work on a second-generation in-house AI accelerator, the Maia 300, intended to reduce Azure's reliance on Nvidia GPUs for Copilot and OpenAI workloads, per The National CIO Review.

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Tom Whitfield
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Microsoft has begun work on a second-generation in-house AI accelerator, the Maia 300, with the explicit goal of reducing the Azure fleet's reliance on Nvidia GPUs, according to a brief report from The National CIO Review. The chip is the next step in Microsoft's effort to internalize a larger share of the compute that powers its Copilot and OpenAI workloads.

What Microsoft Has Already Built

Microsoft disclosed its first custom AI accelerator, the Maia 100, in late 2023. The earlier part served mainly as a learning vehicle and a deployment test for limited internal workloads, rather than as a broad alternative to Nvidia's H100 or H200 systems in Azure.

The Maia 100 gave Microsoft its first hands-on experience with AI silicon designed and validated inside its own data center engineering teams. The Maia 300, by contrast, is positioned in the report as a working alternative for production AI inference and training. That shift signals Microsoft moving from an experimental posture to a competitive one.

The available reporting does not include process node, transistor count, packaging, or interconnect details for the new part. Microsoft has not stated when the chip will tape out, which foundry will manufacture it, or how many units it plans to deploy.

Why Microsoft Is Building It

Azure's revenue growth has tracked closely with the build-out of GPU clusters for OpenAI and enterprise customers. Each new Nvidia generation has arrived with constrained supply and a premium price tag. Microsoft, like its hyperscaler peers, has concluded that being a top-tier customer is not the same as controlling its own roadmap.

Reducing the share of Nvidia silicon in the fleet would give Microsoft more leverage in pricing negotiations, hedge against GPU shortages, and shorten delivery lead times for new capacity. The reasoning is procurement economics as much as it is technical differentiation.

Nvidia remains the dominant supplier. Even a successful Maia 300 program would not displace Nvidia in the near term; the installed base of H100 and H200 systems runs into hundreds of thousands of units across Azure regions. The Maia 300 is intended to grow alongside that fleet rather than replace it.

How the Market Shifts

A credible Microsoft alternative narrows Nvidia's pricing power at the margin and gives foundry partners a second hyperscaler-scale customer for advanced packaging and HBM memory. It also deepens the demand for high-bandwidth memory from SK hynix and Micron, regardless of whether the compute die comes from a merchant fab or a captive source.

The move also narrows the runway for AMD's MI300 and MI325X roadmaps inside Azure. Microsoft was an early AMD customer, and further internalization of AI silicon would reduce the field of buyers still seeking a merchant alternative to Nvidia at hyperscaler volumes.

Taken together, three vectors are converging: Nvidia's pricing power, hyperscaler capital discipline, and HBM supply concentration. Each of those now has a second source asking to be taken seriously.

What Remains Unclear

The available report does not state when the Maia 300 will tape out, which foundry will manufacture it, or how many units Microsoft plans to deploy. Performance targets, interconnect choice, and the rollout schedule relative to Nvidia's Blackwell generation also remain undisclosed.

Until Microsoft files public earnings commentary with concrete deployment figures, those numbers are analyst estimates rather than company guidance.

The takeaway: Microsoft's Maia 300 turns a learning project into a procurement lever, and the AI accelerator market is no longer a single-vendor story.

Source: Google News: AI chips

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Tom Whitfield

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Staff writer covering companies, deals and strategy in Semiconductors, chip manufacturing, hardware, AI compute at Chip Dispatch.

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