The binding constraint on AI chips is no longer transistor density: power delivery, memory bandwidth and advanced packaging now set the ceiling on performance, according to a Forbes analysis published under the headline "Power, Memory And Packaging, Not Transistors, Now Limit AI Chips."

The argument marks a structural shift in how the industry talks about progress. For two decades, the milestone that mattered was the next process node — smaller transistors, more of them per square millimeter, better dollars-per-compute. Forbes' assessment says that logic scaling, while still advancing, has stopped being the limiter that decides whether an AI accelerator actually delivers faster training or inference.

What has replaced the transistor as the bottleneck?

Three physical constraints now dominate, per the analysis:

• Power. Feeding and removing heat from densely packed AI silicon has become the first-order engineering problem. A chip can only compute as fast as its power delivery network and cooling allow.
• Memory. Compute throughput has outrun the memory subsystem's ability to feed it. Insufficient bandwidth between processing elements and memory leaves expensive logic sitting idle.
• Packaging. The technologies that stitch logic and memory together — advanced substrates and multi-die integration — have become the scarce, hard-to-scale capability that determines real-world performance.

The common thread: all three sit above or around the transistor, not inside it. Progress in AI silicon now depends as much on the system around the die as on the die's logic density itself.

Why does this matter commercially?

If transistors are no longer the limiter, value in the supply chain migrates. Companies that control HBM-class memory, power delivery components and advanced packaging capacity gain pricing power relative to those that only push logic nodes. That reframes who captures margin across the AI accelerator stack.

It also reframes the competitive race. A rival that trails on the leading logic node can still compete if it wins on packaging integration and memory proximity — the factors that, per the Forbes analysis, actually cap performance today.

For chipmakers, the calculus of capital allocation shifts accordingly. Investment in packaging lines, memory supply agreements and thermal engineering now buys performance gains that another logic-node step may not.

What does it mean for the node race?

The analysis does not argue that process development has stopped mattering. It argues that logic scaling has slipped from being the primary constraint to being one input among several. When an accelerator underperforms, the explanation is increasingly found in watts, bandwidth and integration — not in gate pitch.

That is a meaningful change for how product roadmaps read. Announcements of finer nodes will matter less to buyers than claims about memory capacity per package, interconnect bandwidth and power efficiency per operation.

What comes next?

If Forbes' framing holds, the next round of AI-chip differentiation will be fought over packaging capacity, memory supply and power engineering — and suppliers in those layers are positioned to capture more of the value that transistor scaling used to claim.

This article is based on reporting and analysis originally published by Forbes.