Intel plans to build its next-generation Razor Lake processors on TSMC's 2nm-class N2X process, according to a report from Wccftech — a move that would put Intel in direct competition with AMD for the same, already constrained, leading-edge wafer capacity.

The report, which has not been confirmed by either Intel or TSMC, claims Razor Lake will be fabricated on N2X, an enhanced variant of TSMC's N2 node family. If accurate, the decision would mark another significant outsourcing step for Intel, which has repeatedly turned to TSMC for tiles it cannot economically produce in-house at advanced nodes.

The competitive implications center on capacity rather than performance. TSMC's first-generation 2nm capacity is expected to be tight through its initial ramp, with Apple historically claiming the lion's share of each new leading-edge node's early output. Adding Intel as an N2X customer would leave AMD — TSMC's largest high-performance computing CPU customer at advanced nodes — competing for a smaller share of a fixed wafer pool, according to the report's framing.

That dynamic has a commercial logic. When two direct x86 rivals source from the same foundry at the same node, allocation becomes a competitive weapon. A customer that secures larger early volumes can launch sooner, ship more units, and hold pricing discipline; a customer squeezed on allocation faces delayed ramps and thinner availability at launch. The Wccftech report suggests AMD would be the party squeezed.

For Intel, the reported arrangement would continue a tile-based strategy already in place across its client lineup, in which the company mixes internal Intel Fab process tiles with externally sourced compute or graphics dies. Razor Lake, as the successor generation in Intel's client roadmap, would extend that hybrid approach to TSMC's most advanced node.

For AMD, the risk is asymmetric. Unlike Intel, AMD owns no leading-edge fabs and depends entirely on TSMC for its premium CPU and GPU products. Any large new tenant at N2X directly constrains AMD's ability to secure wafers for its own next-generation server and client chips. AMD has not commented on the report.

Neither company has verified the claim, and Intel's final packaging and tile sourcing decisions for future generations have shifted before as internal process roadmaps evolve. Intel Foundry's own 14A and 18A-family nodes remain candidates for future client products, and the company has stated publicly that it will balance internal and external manufacturing based on economics and capacity.

Still, the report lands at a moment when leading-edge foundry capacity is genuinely scarce. TSMC is ramping N2 across a limited set of facilities, and demand from smartphone, HPC, and AI accelerator customers is expected to absorb early output. In that environment, an additional x86 customer at N2X would intensify competition not just for wafers but for advanced packaging, testing, and CoWoS-adjacent capacity that leading-edge CPUs increasingly require.

If the report holds, the practical consequence would likely show up in launch timing and supply availability for both companies' next client platforms in 2026 and beyond — with the winner determined less by architecture than by who secures allocation at TSMC's 2nm-class fabs.