Synaptics Puts Google's Coral NPU Architecture on Two New Edge AI Boards

Synaptics has shipped two development boards built around NPUs licensed from Google's Coral core architecture, with the flagship Coralboard SL delivering 1 TOPS of neural processing on the company's SL2619 AI SoC. The SL board is available now, and it pairs the accelerator with a dual-core Arm CPU complex, 2 GB of DDR4 memory, and a compiler stack rooted in the open-source MLIR project.

The move matters because it pushes Google's Coral NPU design beyond Google's own edge modules and into a merchant silicon vendor's product line. Synaptics brands the accelerator as its Torq NPU, and it now spans a performance range from 200 GOPS to 1 TOPS across a family of SoCs aimed at vision and audio AI at the edge.

What is inside the Coralboard SL?

The SL2619 SoC combines a pair of 2-GHz Arm Cortex-A55 application cores with a 200-MHz Cortex-M52 that includes Helium vector extensions for real-time tasks. The Cortex-A55 cores can host a full operating system such as Yocto Linux, while the M52 core can run a real-time operating system like FreeRTOS or Zephyr.

The NPU itself incorporates RISC-V cores internally, a detail that reflects how accelerator vendors now mix ISAs within a single chip to balance control, power, and throughput. Synaptics states the SL2619 can run large language models locally on the board.

The board-level feature set targets embedded vision and audio developers:

• 2 GB of DDR4 DRAM
• CSI and DSI ports for cameras and displays
• QWIIC and mikroBUS connectors for sensor expansion
• An M.2 slot for Wi-Fi and Bluetooth modules

Both boards share a hardware root-of-trust security subsystem, which Synaptics positions as a baseline feature across the family. In short, the SL board packages a complete Linux-class edge AI system on a single development platform.

How does the low-power SR variant differ?

The second board, the Coralboard SR, runs Synaptics' SR250 SoC and trades performance for power efficiency. It replaces the dual Cortex-A55 cores with a single 800-MHz Arm Cortex-M85 and streamlines the NPU to 400 GOPS.

The SR board keeps the same interface set as its larger sibling and adds NOR flash memory plus a MicroSD card slot for storage. This positions the SR board for always-on applications where a full Linux stack would consume too much power. The takeaway is simple: one architecture, two power points, one software stack.

Where do the SR200-family SoCs fit?

The SR250 sits at the top of a broader SR200 portfolio that Synaptics has segmented by workload. The SR210 targets very low power, always-on voice and sensing applications with a 200-GOPS NPU. The SR230 adds vision, display, and optional audio support at 300 GOPS. The SR250 rounds out the line at 400 GOPS with dual vision and display paths.

That segmentation lets designers pick a performance tier without changing toolchains or vendor relationships. Each step in the family trades accelerator throughput against the feature set around it.

Why build the compiler on MLIR?

All of the NPUs in both families run through Synaptics' Torq AI engine, supported by the company's SDK. The compiler inside that stack builds on MLIR, the Multi-Level Intermediate Representation subproject hosted under the LLVM compiler project.

As the MLIR documentation describes it: "The MLIR project provides a modular and extensible intermediate representation (IR) framework intended to facilitate constructing domain-specific compilers and improve compiling for heterogeneous computing platforms." MLIR already supports multiple AI compiler ecosystems, including runtimes such as TensorFlow.

The choice has commercial weight. By anchoring the toolchain on an open-source IR framework rather than a proprietary one, Synaptics reduces the porting cost for developers who already target TensorFlow-based flows, and it gives the company a compiler foundation that the wider LLVM community maintains. For customers, that means the software investment tracks an open ecosystem rather than a single vendor's roadmap.

What does this mean for edge AI hardware?

The two Coralboard launches show a clear pattern in edge AI silicon: license a proven NPU architecture, wrap it in a tiered SoC portfolio, and standardize the software on open compiler infrastructure. Synaptics gets a proven accelerator design in Google's Coral core architecture; Google gets its edge AI architecture distributed through a second silicon channel; developers get hardware they can evaluate today, with the SL board already on sale.

With performance tiers from 200 GOPS to 1 TOPS now covered under a single Torq and MLIR-based toolchain, Synaptics has laid out a path for customers to scale edge AI designs from always-on sensing up to local LLM inference without leaving one software stack.