Tensordyne has taped out a 138-billion-transistor AI inference accelerator on TSMC's 3-nanometer process. The Napier chip converts matrix multiplication to logarithmic addition. It cuts power draw to 300 watts from the 1,200 watts Nvidia's "Blackwell" B300 GPU accelerator consumes.

Why convert matrix math to logs?

Multiplying matrices is hard even for matrix multiplier hardware. Adding numbers is easier. Napier converts tensor values to logarithms, adds them, and avoids the multiplication overhead entirely. The shift yields more than an order-of-magnitude improvement in performance, price, and power versus hybrid inference systems from Nvidia and Amazon Web Services, the company claims.

The 3 nm device packs 48 logarithmic cores built around 128-by-128 systolic arrays. Each chip delivers 2.1 petaflops at dense FP8 precision. It carries 144 GB of HBM4 memory across four stacks. On-chip SRAM adds 256 MB at 40 terabytes per second.

Anand said the architecture hinges on Broadcom's role as chip shepherd. "As long as we are within lead times, we can get any volumes customers need," Anand stated. Broadcom ranks as the third-largest buyer of HBM memory globally and the third-largest buyer of TSMC wafers.

What does the rackscale system look like?

Nine Napier chips share a 1U compute tray with a 40-core Intel Xeon host. Eight trays form a 72-chip pod at 19 petaflops of FP8 throughput. The pod carries 1.3 TB of HBM4 and 2.25 GB of SRAM at 360 TB/sec. TDNLink, Tensordyne's proprietary interconnect, links the pod with sub-microsecond hop latency.

A full rackscale configuration spans four pods joined over Ethernet. It hits 608 petaflops at FP8. The system holds 42 TB of HBM, 74 GB of SRAM, and 266 TB of flash. Aggregate TDNLink bandwidth reaches 275 TB/sec. Total power draw is 120 kilowatts and runs on air cooling.

How does Napier stack up against Nvidia and AWS?

Anand claims the Napier rackscale can drive 1 billion tokens per second from 350 racks. Comparable throughput from an all-GPU system would require roughly 2,000 racks and 30 percent more power. The same datacenter floor space can push through six times as many tokens.

Tensordyne also compared a combined Nvidia "Rubin" GPU prefill plus Groq 3 LPU decode stack against AWS Trainium3 prefill plus Cerebras CS-3 decode. Pricing data from AWS remains incomplete. If Napier performance holds, prices across the inference tier will have to fall.

Who is behind the chip?

Tensordyne started as Recogni in September 2017, building inference systems for the automotive sector. Co-founders RK Anand and Gilles Backhus hired Marc Bolitho as chief executive officer in July 2022. The company pivoted toward datacenters at that point. Tensordyne has since grown to 120 employees and raised $176 million across three funding rounds.

Backhus confirmed per-rack processor counts. "Per rack, we have 320 Xeon cores, and then we have another 4,608 RISC-V cores per rack," he said. The RISC-V cores handle token-loop tasks, including mixture-of-experts routing. The Xeon manages inference serving and 200 Gb/sec Ethernet uplinks.

When does Napier reach customers?

Cloud access to Napier engines opens by the end of 2026. Beta TDN Pod systems land with customers in the first quarter of 2027. Volume shipments begin at the close of the second quarter of 2027.

What does this signal for Nvidia?

If logarithmic matrix math delivers the claimed gains, Nvidia's inference margins face the same disruption Sun Microsystems endured against x86. Broadcom-supplied HBM4 access removes the historical supply ceiling. Pricing pressure on the inference tier becomes structural by mid-2027.