TSMC plans to scale production on its 2 nm-class process technology to 120,000 wafers per month by the end of 2026, according to a report from TechPowerUp. The figure represents a substantial step up in output for the company's most advanced node and sets a concrete marker for how quickly the foundry expects leading-edge capacity to come online.

The target matters because volume, not just yield, determines who captures the leading-edge market. A capacity ceiling of 120,000 wafers per month gives TSMC room to serve multiple large customers simultaneously on the same node — something smaller competitors struggle to offer. For fabless chipmakers planning flagship silicon for 2026 and beyond, that headroom reduces the risk of allocation bottlenecks during the first two years of the node's life, when demand for leading-edge wafer supply historically runs hottest.

The number also frames the economics of the transition. Each successive node raises wafer costs, so volume commitments of this scale only make sense if customer demand is both confirmed and growing. A ramp plan to 120,000 wafers per month signals that TSMC's customers have already committed to moving their highest-value products — mobile processors, high-performance computing chips, and AI accelerators — onto the 2 nm platform rather than stretching previous-generation processes for another product cycle.

The timing puts the full-scale output roughly two years after initial production begins, a cadence consistent with how leading-edge nodes typically mature: early low-volume runs for first movers, followed by rapid capacity expansion once yields stabilize and additional customers qualify their designs. By the end of 2026, TSMC would be positioned to treat 2 nm not as a boutique process but as a mainstream volume node.

That distinction carries competitive weight. Samsung Foundry and Intel are both racing to win leading-edge orders, and one of their central arguments is that customers need a second source of advanced capacity to hedge supply risk. A 120,000-wafer-per-month footprint strengthens TSMC's counterargument: that it alone can absorb the volume requirements of the largest chip designers without forcing them to split designs across fabs or accept slower ramps.

For the broader supply chain, the plan implies sustained demand for advanced lithography, deposition, and metrology tools through 2026, since each expansion tranche requires a new wave of equipment installation. Equipment suppliers and materials vendors typically see order momentum build ahead of such capacity milestones, and a publicly framed target of this size gives the ecosystem a planning horizon.

The report describes the 120,000-wafer figure as a target for the end of 2026, which places it in the category of roadmap guidance rather than achieved output. Capacity plans at leading-edge nodes have historically flexed with demand: TSMC expanded its N3 family faster than originally guided when AI-related demand surged, and it has also trimmed utilization when end markets weakened. The 2026 figure should therefore be read as the foundry's current best estimate of committed demand, subject to revision as orders firm up.

What is not in question is the direction. TSMC continues to bet that the migration to 2 nm-class technology will pull the industry's largest and most expensive designs onto its newest wafers, and it is building the physical capacity to prove it. If the ramp holds to schedule, the end of 2026 will mark the point at which 2 nm stops being a launch node and becomes the volume baseline for the company's advanced-process business.