Volantis, a San Francisco semiconductor startup, has closed an $88 million Series A to build an AI inference architecture it claims lifts the memory capacity-bandwidth tradeoff that constrains today's GPUs and HBM-based systems.

Lachy Groom and Abstract Ventures co-led the round, with participation from John Doerr, VXI Capital, Triatomic and Susa Ventures. Angel investors include Dwarkesh Patel, Naveen Rao and Sholto Douglas. The company announced the financing Oct. 1, 2026.

Volantis is designing its first system, A-1, to run models exceeding 20 trillion parameters at up to 10,000 tokens per second per user while cutting inference cost per token. The company plans to deliver its first integrated inference engines to customers in 2027. Those figures are design targets on a product roadmap, not measured results: A-1 has not yet shipped.

Attacking the memory wall

Large-model inference demands both memory capacity to hold the model and bandwidth to feed the compute engine continuously. Existing silicon forces a compromise between the two. On-chip SRAM delivers high bandwidth but limited capacity, constraining model size and context windows while driving up cost and power. GPUs and other HBM-based systems offer more capacity, but their bandwidth caps how fast they can serve increasingly large models. Even newer approaches such as 3D DRAM sit on the same tradeoff curve, according to the company.

Volantis says A-1 will increase memory capacity and bandwidth simultaneously by nearly two orders of magnitude, letting larger models run at much higher inference speeds. The claimed payoff is faster agent workflows — a coding agent finishing a task in two minutes instead of 30, for example.

"As AI agents take on more work, how fast they complete that work will increasingly determine how fast companies can operate," said Tapa Ghosh, CEO and co-founder of Volantis. "Today's hardware forces a tradeoff between running the largest, most sophisticated models and running them fast. We started Volantis to eliminate that tradeoff."

Photonics built for chip-to-memory links

The technical bet is a new category of photonic interconnect designed specifically to connect compute chips to memory. Volantis' optical fabric pools large numbers of memory chips into a unified resource, aggregating their bandwidth as capacity scales, and uses lower-cost off-chip memory to hold down system cost.

That is a different problem from the chip-to-chip optical links already deployed inside data centers. Chip-to-memory connections require more than 100 times as much data to travel over much shorter distances, imposing distinct energy and cost requirements, the company said.

Volantis built its photonic platform around custom micro-VCSELs rather than external lasers. The company says the choice draws on the existing gallium arsenide VCSEL supply chain and avoids indium phosphide supply constraints — a relevant consideration given tightening InP capacity for optical components. The micro-VCSELs are small, temperature-stable and low power, enabling end-to-end links that consume less than one picojoule per bit. Volantis plans to disclose additional architectural details as A-1 moves toward commercialization.

Founding pedigree

The founding team includes semiconductor and photonics veterans from NVIDIA, AMD, Broadcom and Ayar Labs. Their prior work spans the first CoWoS product — the chip-on-wafer packaging technology that now underpins NVIDIA's high-end AI accelerators — the first high-volume tunable VCSELs, and early silicon photonics co-packaged optics systems.

The Series A will fund development and commercialization of A-1 and its photonic memory architecture, including engineering headcount growth and the move toward customer deployments.

Volantis enters a market where HBM supply remains dominated by Samsung, SK hynix and Micron and inference cost per token is the metric cloud providers watch most closely. If the company's chip-to-memory optical fabric delivers its claimed capacity-bandwidth scaling on schedule, A-1's 2027 debut will offer an early test of whether photonics can move from inter-rack links into the memory subsystem itself.