A 200-case thermal design sweep that once burned 16 hours on a legacy workflow now runs in roughly an hour, with setup in under a minute — the clearest number yet that EDA is being rebuilt around 3D-ICs rather than monolithic chips. Vinci CEO Hardik Kabaria, who supplied the figure, adds that the physics analysis scales near-linearly beyond 10 billion degrees of freedom. That's the commercial stakes in one sentence: multi-die AI silicon is forcing tool vendors to co-optimize across chip, package, board and system before customers tape out.

The pressure comes from the top of the market. Nearly every AI accelerator has crossed a threshold where the hardest problems no longer live inside the chip, Microsoft vice president of AI silicon engineering Artour Levin said at DAC 2026. "They live at the system boundaries."

His reasoning is blunt. "A standalone chip is not very beneficial for AI because very few things can be run on a single chip," Levin said, noting that EDA tools designed 30 or 40 years ago were built to design chips, not systems.

Why did the old toolchain stop working?

The design toolchain grew up around clean abstraction boundaries — cell, block, chip — with physics handled as episodic, domain-by-domain validation at the end, Kabaria said. That model breaks when heat, stress and electrical behavior move across the whole physical stack, because the physics insight arrives after the decisions that needed it are already made. His prescription: "deterministic, solver-accurate physics that's continuously available across chip, package, board, and system — treating physics as infrastructure rather than a late-stage checkpoint."

Synopsys R&D executive director Henry Sheng frames the vendor dilemma: decades of embedded knowledge work in isolation but not necessarily cross-domain. "How do you manage not to try to boil the ocean?" he asked. "You have to reinvent how you put things together to maintain coherency, so you don't have different data representations and terminologies for the same thing across domains."

Keysight EDA general manager Nilesh Kamdar points to floor-planning, where budgets for loss, signal path and power delivery now have to be negotiated up front for complex 3D environments, leaving little room to renegotiate later.

What are customers actually living with?

Intel's vice president of semiconductor R&D for advanced packaging, Lalitha Immaneni, described a design review that took 10 days of back-and-forth across incompatible tool formats — ending in three color-coded pictures and the need to "bring 10 PhDs in a room." Her ask: EDA tools should agree to a CAD-neutral format so extractions stop becoming complex and customers can pick best-in-class tools from each vendor.

Broadcom distinguished engineer AJ Tufano is more succinct. "We have been living in pain for probably the last five or six years," he said. "We're getting by, we're surviving, we're producing chips, but we can do a lot better." In custom accelerators, fundamental architectural changes arrive every six months, sometimes every three, and 3.5D integration is a large part of that pace.

Qualcomm senior director of engineering Venu Sanaka says exploration is the bottleneck — bump locations, TSVs and thermal trade-offs aren't fast enough within a one-year design cycle, so partitioning analysis needs to start three to six months earlier with early trade-off mechanisms. Moving one block between dies in different technologies is still fully manual, he said: floorplan in 2D, assemble, analyze.

Where does agentic AI fit?

Cadence faced the build-versus-augment question three or four years ago. Customer feedback then: "We have a hundred 2D designers. We don't have any 3D designers, so whatever you build, make sure those hundred people can adapt," said Vinay Patwardhan, product management group director at Cadence. The company built on its foundry-qualified, industry-standard tools, made them 3D-aware, and now layers an agentic flow on top, with what he calls tremendously improved exploration capabilities.

Keysight's latest 3D floor-planning tools let architects toggle via-layer depth or package materials with a few clicks and see the electrical impact, with IR drop, power integrity and thermal multiphysics coming soon. Siemens EDA's vice president of R&D Jeff Dyck reports that setting research targets and benchmark suites for agents — auto fine-tuning, auto distillation — is "working extremely well for building better tools."

Startups are going further:

• ChipAgents — scalable agentic workflows from die to advanced packaging, with tuned customer "brains" aiming to compress months of packaging analysis into a day, said chief product officer Solaiman Rahim.
• Architect Labs — spec-level agents that assemble UCIe interfaces and Arm cores and formally verify as they build, "elevating you from an RTL engineer to a human architect," said sales head Dan Ganousis.
• Rise — two-way spec-to-RTL models that run 30x faster than RTL, enabling immediate verification and rapid memory-bandwidth or node exploration, said CEO Badru Agarwala.
• ITDA — a South Korean no-code, drag-and-drop tool that shifts DFT logic to the earliest RTL stage, said strategy planner Jihwan Lee.
• Suitera — multi-physics simulation at extremely high speeds; co-founder Yehea Ismail says only deep innovation solves the industry's accuracy-versus-speed crisis, after seven years of development.

Arteris's Insaf Meliane adds the caveat the industry repeats like a mantra: AI-generated decisions must be explainable, traceable and validated against deterministic EDA engines before signoff.

What happens next?

Arteris chief product and marketing officer Michal Siwinski puts the trajectory plainly: "Chiplets are given, 3D packaging is a given, and everything is going to go vertical" — with the open question being whether logic dies follow memory dies into true 3D cubes. Synopsys's Sheng argues non-incremental change requires EDA, design and manufacturing moving in concert, not each marching alone. Until then, vendors and their customers will keep shipping phenomenally successful chips through flows everyone agrees are sub-optimal.