Researchers at TU Munich, the University of Modena and Reggio Emilia, and Applied Materials have published a physics-based framework that compares two future transistor architectures side by side: complementary FETs at the A7 node and nanosheet FETs at A10. The paper, posted as arXiv preprint 2609.15326 in September 2026, carries the title "System-Technology Co-Evaluation of A7 CFET and A10 NSFET Technologies from Cell Parasitics to Chip Reliability."

The work matters because the industry lacks a common yardstick for these two nodes. A7 CFET and A10 NSFET sit at different points on the roadmap, and most published studies evaluate them with different device assumptions. This team deliberately used one device model for both. That choice lets them isolate what parasitic resistance and capacitance actually do at each stage of the design flow.

The authors are explicit about the method. "Our flow links calibrated device models, optimized standard-cell generation, automated GDS-to-TCAD conversion enabling accurate 3D parasitic RC extraction, full RTL-to-GDS implementation for an AI accelerator, multiphysics thermal analysis, and physics-based bias temperature instability (BTI) aging evaluation," they write in the abstract.

What does the flow actually cover?

The pipeline spans the full distance from transistor to chip. According to the abstract, the chain includes:

• Calibrated device models shared across both technologies
• Optimized standard-cell generation
• Automated GDS-to-TCAD conversion for 3D parasitic RC extraction
• Full RTL-to-GDS implementation of an AI accelerator
• Multiphysics thermal analysis
• Physics-based BTI aging evaluation

This is a system-technology co-evaluation, or STCO, approach. STCO treats the chip and the process technology as one optimization problem rather than two separate ones. The authors describe their flow as "thermal- and aging-aware," which signals that heat and device degradation enter the assessment before sign-off, not after.

Why compare A7 CFET against A10 NSFET at all?

The pairing reflects where leading-edge logic is heading. Nanosheet FETs are the established successor to FinFET, while CFETs stack the n-type and p-type devices vertically and target a later, denser node. Comparing A7 CFET with A10 NSFET asks a practical question: does the stacked architecture at A7 deliver a net gain over a less exotic device one node earlier, once parasitics, heat and aging are counted?

The shared device model is the paper's control variable. "Using the same device model for both technologies, we can isolate the impact of parasitic RCs and design at different levels of the design flow," the authors state.

What the paper does not say

The preprint excerpt available does not report final numbers. It names no RC values, no thermal results, no aging deltas and no power or area conclusions for the AI accelerator test case. Readers should treat this as a methodology paper with results behind the abstract, not a benchmark verdict. Whether A7 CFET wins on net chip-level merit remains unstated in the public excerpt.

The test vehicle is also specific: one AI accelerator, implemented RTL-to-GDS. Findings may not transfer directly to other design classes. The paper itself frames the contribution as the flow, not a universal ranking of the two nodes.

The author list gives a sense of the collaboration's scope. Benkhelifa, Mahdi, Leon Mayr, Hadi Nour Eddine, and Hussam Amrouch represent the TU Munich side; Andrea Padovani and Luca Larcher are affiliated with the University of Modena and Reggio Emilia and Applied Materials. Larcher and Padovani have long published on physics-based reliability modeling, and Amrouch's group at TUM focuses on aging-aware design.

The preprint is dated September 2026 and is available on arXiv under identifier 2609.15326.

Why it counts for roadmaps

For foundries and design teams, an evaluation flow of this kind sets the terms of the A7-versus-A10 debate. If calibrated models show parasitic RC or thermal limits eroding CFET's density advantage, architecture decisions at those nodes shift. The next signal to watch is whether the full paper's numbers on the AI accelerator hold up the case for stacked devices once BTI aging enters the ledger.