Semiconductor Engineering has published a technical analysis examining how complementary FET (CFET) device architectures can transition from laboratory research toward high-volume manufacturing. The piece focuses on novel integration modules and the standard cell configurations that govern logic density and performance at advanced nodes.

CFET designs stack n-type and p-type transistors vertically on a single footprint, a structural shift from the planar, finFET, and gate-all-around (GAA) architectures that have anchored logic scaling for two decades. The Semiconductor Engineering analysis frames the transition as a sequencing problem: deciding which integration steps must mature first, and which standard cell layouts can absorb the new device geometry without disrupting existing design flows.

What integration challenges does the article address?

The analysis centers on the modules that build the dual-tier device stack: deposition, etch, bonding, and isolation steps that must hold tolerance across two layers of active silicon rather than one. The piece examines how these modules interact with buried power rail and backside power delivery schemes that foundries are introducing at the A14 (1.4nm) node and beyond.

Yield is the implicit constraint. Each new module adds process steps, and each step compounds variability. The article looks at how proposed CFET flows attempt to keep the module count manageable while still delivering the scaling benefit that defines the architecture's commercial case. Specific density targets are not confirmed in the piece.

How do standard cells change under a stacked topology?

Standard cell libraries define the height, width, and pin placement of every logic gate in a chip. With CFET, the available cell height drops because two devices now occupy the footprint of one. The Semiconductor Engineering piece evaluates candidate cell configurations that exploit the stacked structure while preserving routing channels for signal and power.

Designers face trade-offs between cell height, drive strength, and the number of fins or nanosheets per tier. The article discusses configurations in which the upper and lower transistors size independently, allowing cell designers to balance pull-up and pull-down strength without the area penalty that planar and GAA cells incur.

Who drives CFET development?

Imec has led public CFET research through its beyond-2nm and A14 demonstrators, with participation from the major foundries and integrated device manufacturers. TSMC's N2 (2nm) node uses GAA nanosheet transistors, and the company's published roadmap points to A14 and A10 (1nm-class) generations as candidates for stacked-device introductions. Samsung has published CFET research tied to its 2nm and 1.4nm nodes, and Intel's 18A and 14A process generations incorporate backside power delivery — a complementary prerequisite for stacked devices that the Semiconductor Engineering piece identifies as essential.

The article stops short of confirming which foundry will introduce CFET first, or whether the architecture reaches production within this decade.

What remains unresolved?

Three questions hang over the CFET roadmap. First, whether additional process complexity arrives at acceptable cost. Second, whether EDA tools and standard cell libraries re-engineer fast enough to support a production node. Third, whether the thermal profile of a stacked device dissipates heat generated by two active tiers operating in close proximity.

The Semiconductor Engineering analysis treats these as integration problems rather than physics problems. The piece's central message: the industry's next scaling step depends less on novel materials than on getting the module sequence and cell library right.

If the A14 generation ships with CFET blocks in limited form — as embedded memory or analog companions to a GAA logic baseline — the architecture's commercial viability faces testing before A10 volumes arrive. The piece leaves that timing decision to the foundries.