Ten gigawatts: that is the scale of the collaboration OpenAI and Broadcom announced in October 2025, the partnership behind Jalapeño, OpenAI's first inference chip, which moved from initial design to tape-out in nine months before its June 2026 unveiling.

The deal anchored the closing executive panel on September 22 at the Global Semiconductor Alliance's U.S. Executive Forum in Menlo Park, before more than 150 semiconductor executives. Moderating was Patrick Moorhead of Moor Insights & Strategy, whose clients include AMD, Broadcom, Samsung, Nvidia and Qualcomm.

On stage with him were Paul Cho, president of Samsung Semiconductor; AMD CTO Mark Papermaster; Broadcom Semiconductor Solutions Group president Charlie Kawwas; and OpenAI vice president of hardware Richard Ho.

What Has Replaced The Transistor As The Bottleneck?

Ho tied it to deployment economics: "Power is the limiting factor, and a chip aimed at a known set of workloads can be optimized across models, software and silicon to deliver the most intelligence per watt." At OpenAI, the custom part complements the merchant GPUs it keeps buying, it does not replace them.

How Has The Unit Of Purchase Changed?

The unit of purchase is no longer a chip or a rack. Ho allocates power by workload across multiple OpenAI campuses. Kawwas said a single gigawatt of training capacity is no longer sufficient; the new baseline sits at two to four gigawatts per cluster, with single campuses of five to 10 gigawatts expected by 2031.

When buyers plan in gigawatts, chip design becomes system co-design across memory, logic, packaging, networking, and power, settled at the architecture-definition phase rather than in procurement.

Papermaster framed it simply: power is performance. He said the latest process node still delivers a per-watt gain, but it costs more and takes longer to bring up. Most power goes to moving data, which drove AMD to chiplets and 3D stacking. AMD's Venice CPUs ship in six variants, including one aimed at agentic AI workloads.

Why Is Memory Now Page One Of Every Design?

Cho named memory as the constraint that could reorder the industry by 2031. His line of the night: "Memory used to be one chapter in the computer architecture textbook, and by 2031 it will be the first page of every design."

His numbers track UC Berkeley's "AI and Memory Wall" research. Peak server compute has risen about 60,000-fold over 20 years; DRAM bandwidth has risen about 100-fold. The implication: design backward from the bandwidth curve and seat the memory partner in the architecture review, not at procurement.

The mechanism surfaced in a Signal65 evaluation of AMD's MI355X against Nvidia's B200. At high concurrency and long context, the larger high-bandwidth memory capacity turned a 17% deficit into a lead of up to 1.96x. Cho argued HBM is no longer a commodity; Moorhead countered that JEDEC-standard memory at the pin remains interchangeable, with strategic value residing in custom logic base dies under HBM4 stacks and in compute-under-memory designs.

What Makes The Substrate The Next Choke Point?

Kawwas named a pressure point few outside packaging discuss. The back-end IC substrate, the layer that carries chip connections to the board, has run 10% to 15% of chip cost, but he expects it to be the choke point for the next five years. Today's leading chips are designed at part sizes of 10,000 to 15,000 square millimeters, against the 1,000 to 2,000 square millimeters the seven substrate suppliers are accustomed to handling.

Broadcom is responding by entering substrate production through a partner facility in Singapore, planned to start during its fiscal year ending late in 2027. On the OpenAI program, Broadcom's tape-out cycle has dropped from 15 to 18 months to nine, a margin Kawwas said buys at least one extra generation every three years against 12- to 18-month competitors.

What Still Has To Prove Out?

Three items on Moorhead's watchlist:

• No first-generation custom AI chip has dominated out of the gate, so Jalapeño's real test is production tokens at gigawatt scale in 2027.
• HBM qualification runs about a year, so nine-month design cycles now outrun memory validation timelines.
• Samsung's Taylor, Texas fab, slated for customer production in 2027, slipped from an end-of-2026 target, leaving a second source on paper until qualification completes.

Ho said AI has compressed OpenAI's design cycle more than his team expected, turning engineers into "super engineers" rather than replacing them. Papermaster's rule at AMD: agentic AI runs design-space exploration, while accountability stays with the human engineer.

Moorhead's prescription for parts due in 2028: seat the memory and packaging suppliers at the architecture review, plan for qualification cycles that now exceed design cycles, and qualify a second geography.

If the consensus in Menlo Park holds, the next AI silicon generation will be graded on watts per teraflop and on bandwidth at the die edge, not on transistor counts, and the suppliers controlling power delivery, HBM stacks, and substrate capacity will set the pace.