Everspin has demonstrated x86 server memory expansion using its PERSYST MRAM connected to a Supermicro server across a CXL link — a first for the MRAM supplier.

The demo system paired a Supermicro AS-1116CS-TN server with a 32-core AMD EPYC 9355 CPU and an AMD Alveo U250 FPGA carrying a Wolley CXL controller. Four Everspin PERSYST 1GB DDR4 MRAM UDIMMs mounted on the card delivered a fast persistent buffer and cache tier, with cache-line-level, nanosecond-class access and writes up to 100x faster than NAND-based solid-state storage.

Everspin CEO and president Sanjeev Aggarwal framed the demonstration as a way to widen MRAM's addressable market. "Everspin has been working with data center customers for 15 years, and we continue to innovate as AI changes the memory needs of systems," he said. "CXL gives us a standard way to bring persistent MRAM to a much broader range of compute platforms. We now have a working system so customers can run their own workloads and measure the benefit for their specific applications."

The MRAM parts in the demonstration belong to Everspin's PERSYST ST-DDR4 family — specifically the 1 Gb EMD4E001G device, a Spin-Transfer Torque (STT-MRAM) component. STT-MRAM stores bits by using spin-polarised currents to flip the magnetic orientation of a cell. The result is a memory that combines attributes from both sides of the storage hierarchy: DRAM-class access speed, NAND-class persistence and virtually unlimited endurance. It is non-volatile and byte-addressable.

CXL (Computer eXPress Link) provides the transport. The initial CXL v1 standard lets server CPUs access shared memory on local accelerator devices using a cache-coherent protocol across the PCIe bus. Crucially, the external memory is addressed with memory semantics — it is not a block-addressed storage device hanging off the host.

Wolley supplied the CXL controller on the Alveo card. Wolley CEO Dr. Bernard Shung said: "Wolley enables memory and storage connectivity through CXL, and this demonstration with Everspin shows how persistent MRAM can be brought into that environment with memory semantics. Together, we are demonstrating a practical way to connect persistent memory through CXL and make it available to today's compute platforms."

One spec detail matters for anyone assessing near-term productization: the Alveo U250's host interface is PCIe Gen3 x16 (8 GT/s), per AMD's U200/U250 datasheet. The card is not a PCIe Gen4 or Gen5 endpoint.

The commercial logic

Everspin's pitch targets system builders assembling x86 edge and small data center AI inferencing servers. In such systems, CXL-connected MRAM could hold AI data such as KV cache blocks, serving reads faster than external SSDs — even SSDs fronted by RDMA-based KV cache software — while keeping that data intact through power failures or system restarts. The design would need no battery-backed DRAM and no flush-to-SSD step before power goes down. Data simply persists.

That persistence argument echoes the one Intel made for Optane. The comparison cuts both ways. Like Optane, MRAM has struggled to break out of specialist, low-volume markets where its relatively high price does not act as a buying barrier. Everspin's demonstration does not change the cost equation; it changes the connectivity equation by giving persistent memory a standardized attach point that didn't exist when Optane fought its losing battle.

The PCIe Gen3 link in the demo is also a constraint on the vision. Serving KV cache blocks for AI inference at competitive latency would, realistically, require CXL running across PCIe Gen5 or even Gen6 links — far faster than the Gen3 interface the Alveo U250 offers today.

Everspin's corporate history tempers expectations too. Founded in 2003, the company has raised a total of $80.3 million, with its last funding round in 2015. It went public in October 2017, and revenues have see-sawed since, on an overall low growth trajectory.

Still, a working system — not a paper architecture — gives Everspin something it can put in front of customers. Aggarwal's point that data center operators can now "run their own workloads and measure the benefit" signals the next phase: qualification cycles that will determine whether persistent MRAM over CXL finds volume deployment in AI inferencing platforms, or joins Optane as another persistent-memory technology that proved the concept without proving the business.