Everspin Technologies (NASDAQ: MRAM) has demonstrated what it calls the world's first Compute Express Link (CXL)-connected MRAM platform at the SNIA Developer Conference (SDC) 2026, a working system that delivers persistent memory with cache-line-level, nanosecond-class access and writes up to 100x faster than NAND-based solid-state storage.

The demonstration, announced Sept. 30 from the company's Chandler, Arizona headquarters, inserts a fast persistent memory tier between DRAM and NAND storage. Everspin says the tier can reduce the time processors and accelerators spend waiting for data and help AI systems run at higher utilization.

The hardware stack is concrete and fully standards-based. Everspin connected its PERSYST 1GB DDR4 MRAM UDIMMs to a Supermicro AS-1116CS-TN server running an AMD EPYC 9355 32-core processor. An AMD Alveo U250 FPGA platform with a Wolley CXL controller bridges the MRAM modules to the host over the CXL interface. At SDC, Everspin and Wolley demonstrated read and write access to the MRAM through CXL under demanding test conditions.

The commercial argument rests on two properties. First, MRAM retains data without power, so the persistent buffer and cache tier survives power interruptions and system restarts without battery-backed DRAM and without flushing data to an SSD first. Second, CXL exposes the memory coherently to standard compute platforms, which lets memory resources be pooled and shared across hosts and persistent capacity be allocated where workloads need it.

For AI systems, Everspin points to two specific applications: checkpointing and persistent key-value (KV) cache. Both benefit from fast, byte-addressable persistence — checkpointing because it removes the write-out penalty to NAND, and KV cache because context data can persist across restarts rather than being rebuilt.

"Everspin has been working with data center customers for 15 years, and we continue to innovate as AI changes the memory needs of systems," said Sanjeev Aggarwal, president and CEO of Everspin Technologies. "CXL gives us a standard way to bring persistent MRAM to a much broader range of compute platforms. We now have a working system so customers can run their own workloads and measure the benefit for their specific applications."

Wolley, which supplies the CXL controller, framed the demo as proof of practicality rather than a roadmap promise. "Wolley enables memory and storage connectivity through CXL, and this demonstration with Everspin shows how persistent MRAM can be brought into that environment with memory semantics," said Dr. Bernard Shung, CEO of Wolley. "Together, we are demonstrating a practical way to connect persistent memory through CXL and make it available to today's compute platforms."

The SDC demonstration extends Everspin's broader push to move MRAM beyond its traditional embedded and standalone niches into new memory architectures, including persistent caching, write buffering and metadata applications in the data center.

The demonstration is a proof point, not a product launch. The 1GB module capacity and the FPGA-based CXL path place this platform firmly in the evaluation category: customers can now run their own workloads on it and quantify the benefit for their specific applications, which is precisely what Everspin is inviting them to do. Whether persistent MRAM tiers move from demo racks into production AI infrastructure will depend on those customer measurements and on how quickly CXL-attached memory gains traction in data center deployments.