Chip Manufacturing

GlobalFoundries to Build Silicon Interposers for TSMC

GlobalFoundries will manufacture silicon interposers for TSMC, Investing.com reports, linking the foundry rivals in advanced packaging amid AI-driven capacity tightness.

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Tom Whitfield
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GlobalFoundries will manufacture silicon interposers for TSMC, according to a report by Investing.com — a deal that pairs the world's largest contract chipmaker with one of its closest rivals on the packaging side of advanced semiconductor production.

The arrangement centers on interposers, the silicon layers that connect logic dies and high-bandwidth memory in multi-chip packages. TSMC has built its CoWoS family of 2.5D packaging technologies on in-house interposer supply, and that segment has been a persistent bottleneck as AI accelerator makers race to secure capacity. GlobalFoundries, which exited the leading-edge logic race at 7nm-class nodes, brings large-format wafer capacity that TSMC can now draw on for this intermediate layer rather than for the compute dies themselves.

Why would TSMC lean on a competitor?

Advanced packaging has moved from a back-end afterthought to a capacity constraint in its own right. Interposers do not require leading-edge transistors — they need good silicon, wide through-silicon via capability and yields at scale. That makes them a natural product for a foundry like GlobalFoundries, whose fabs run mature process nodes. Outsourcing interposer production would let TSMC keep its most advanced capacity focused on logic wafers while widening the packaging pipeline its customers depend on.

For GlobalFoundries, the deal would add a high-volume customer to its specialty portfolio, which already spans RF silicon, embedded memory and power technologies, and would deepen its role in a supply chain segment where demand is growing faster than capacity.

What it signals for the foundry market

A supply agreement between the two companies — TSMC dominant at the leading edge, GlobalFoundries focused on mature and specialty nodes — points to a market where cooperation on packaging and interconnect layers sits alongside competition for logic wafer orders. As multi-die designs become standard for AI and high-performance computing silicon, interposer and packaging capacity decisions will increasingly shape which chipmakers can ship systems at volume.

The report does not specify capacity figures, production sites, financial terms or a start date. If confirmed and expanded, expect advanced-packaging supply tightness — and the pricing power that comes with it — to remain the central commercial dynamic through the current buildout cycle.

Source: Google News: TSMC

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Tom Whitfield

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Staff writer covering consumer brands and retail at Chip Dispatch.

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