A joint research team from Kangwon National University and Harvard University has identified the root cause of interfacial defects at silicon–insulator boundaries, overturning the industry's working assumption that hydrogen content governs interface quality. The results appeared in Advanced Materials, and Professor Eom Han-don of Kangwon National University's Department of Chemical Engineering announced the findings on September 29.

The defects in question sit at the atomic scale, exactly where silicon meets the insulating film in a semiconductor device. They raise current leakage and power consumption, and they shorten device lifetime. For years, the industry's standard answer has been hydrogen thermal treatment: passivating dangling bonds at the interface after the film stack has already been formed.

The Kangwon-Harvard collaboration, working with domestic research institutions, took a different route. Using atomic-level analysis, the team measured defect densities across thin films with varying hydrogen retention. The correlation ran opposite to expectation. Films that retained more hydrogen exhibited more interfacial defects, not fewer. That result pointed away from hydrogen itself as the controlling variable and toward the completeness of the oxide film.

In other words, hydrogen treatment was masking a symptom. The underlying driver of interface quality is how densely and completely the oxide forms in the first place.

The team then tested the implication directly. During plasma atomic layer deposition, they formed a dense oxide film without any separate hydrogen thermal treatment step. The result: interfacial defects dropped significantly. Defect prevention moved from a post-fabrication fix to a property built into the deposition process itself.

The thermal budget is the other headline number. The process forms high-quality interfaces at 150 degrees Celsius. Conventional hydrogen anneals for interface passivation typically demand considerably higher temperatures, which constrains where in a process flow they can be applied. A 150°C route relaxes that constraint, and the researchers highlight the consequence: the technique becomes viable for 3D stacking, advanced packaging, and next-generation semiconductor processes, where layers of differing thermal sensitivity are bonded and processed on top of one another.

For memory and logic roadmaps that are pushing vertically — stacked NAND layers, backside power delivery, chiplet integration — thermal budget and interface quality are coupled problems. Every added interface is a potential leakage path, and every high-temperature step limits the materials that can sit beneath it. A low-temperature deposition that produces clean interfaces by design addresses both constraints at once.

Professor Eom framed the contribution as a shift in methodology. "We presented an interfacial design principle that prevents defects from forming in the first place, rather than addressing them post-fabrication," he said. He added that the work "is expected to enhance the quality and reliability of South Korea's core semiconductor industry."

The claim is grounded in the structure of the finding. Because the team identified oxide film completeness — not hydrogen dosage — as the fundamental factor, process engineers gain a design principle rather than a recipe: tune the deposition to produce a dense, complete oxide, and defect generation falls before any remediation step is needed. The study's experiments were carried out at the atomic scale on silicon–insulator interfaces, the configuration at the heart of MOS device operation.

Commercial deployment is not yet on a timetable; the published work establishes mechanism and demonstration, not a qualified manufacturing flow. But the direction matters. If plasma ALD-grown dense oxides at 150°C can match or beat the interface quality of hydrogen-annealed stacks, passivation steps could be simplified or eliminated in flows where they are currently mandatory — a cost and thermal-budget lever that 3D-stacked devices are positioned to pull first.