50 nm Defects: Hybrid Bonding Pushes Inspection to Its Limits

Hybrid bonding production lines today run at pitches of 4 to 9 µm, and defect specifications for leading-edge processes have already fallen to 50 nm particles. At those dimensions, inspection and metrology tools — optical, infrared, X-ray, acoustic and atomic force — are straining to separate yield-killing defects from harmless topography before the wafers are permanently joined.

Hybrid bonding replaces 35 µm off-chip microbumps with 10 µm pitch or smaller pad-to-pad interconnects directly on-chip. The process joins silicon to silicon, as in future DRAM-DRAM stacks for HBM devices, or even dissimilar pairings such as GaN-on-silicon. It is available on wafer-to-wafer and die-to-wafer platforms, cuts signal delay to negligible levels, shrinks and thins packages, and consumes significantly less power. A single particle, however, can delaminate the top wafer from the one below. The result is catastrophic failure.

Why particles matter so much

"Particles and surface contamination are among the most critical defects in hybrid bonding, as they can prevent contact between bonding surfaces and lead to the formation of voids," said Burhan Ali, product marketing director at Onto Innovation. "Smaller interconnect pitches reduce the tolerance for defects, making even nanoscale particles capable of causing bonding voids. For leading-edge hybrid bonding processes, defect size requirements can be as low as 50 nm."

The process itself is unforgiving. Chemical-mechanical polishing must control copper pad recess to a few nanometers — typically 2 nm to 5 nm below the dielectric — while holding surface roughness near 0.5 nm RMS. Process control must keep that recess within 2 nm across the entire wafer. Just one nanometer of material can decide whether copper pads fuse during annealing.

Four pivotal steps

Bond quality rests on the precision and uniformity of four processes:

• Surface planarization (CMP): nanometer control of topography and copper recess, with slight dishing of several nm that the copper fills back during anneal.
• Surface activation: plasma treatment creates dangling Si-O⁻ bonds, followed by a DI water rinse to hydrate the dielectric (SiCN or SiO₂).
• Precision alignment: face-to-face bonding after both wafers reach copper CMP.
• Thermal bonding: furnace annealing at 350°C for two hours expands the copper and forms permanent Cu-Cu and dielectric-dielectric bonds.

Improper edge roll-off after CMP can distort alignment marks, causing poor contact or voids. Microcracks, scratches and handling damage in the roll-off region carry the same risk.

Pre-bond inspection: full wafer or nothing

Microtronic's applications director Errol Akomer argues macro-inspection must cover every wafer. "By inspecting 100% of the wafers at each mask level, our macro-inspection tool provides a great complement to the micro-inspection tools on the market," he said. Micro tools sample only two to five wafers per lot, he noted, and "in many cases, they're missing some really big defects." In data center and aerospace applications, customers select only the best chips and discard what he called "the walking wounded."

After cleaning, automated optical inspection runs in brightfield and darkfield modes — darkfield catches particles and scratches through scattered light, brightfield isolates slurry residue, pattern defects and surface damage. For topography, Onto Innovation's Maruko Wu explained the division of labor: interferometry measures wafer- and die-level planarity, while optical CD tools and AFM control local height variations of a few nanometers. Bruker, KLA, Onto Innovation and Zygo supply interferometric tools; some offer double-sided systems.

AFM and atomic force profilometry now play complementary roles. AFM delivers localized, sub-nanometer measurement of recess, dishing and protrusion. AFP scans large areas — up to 33 × 26 mm — and can reveal out-of-spec topography even when local AFM scans confirm in-spec roughness and recess. Zeiss, meanwhile, is measuring and correcting surface planarity by inducing local strain in the wafer before backside thinning. "We see increasing market interest in this solution, especially as HCB is used on multi-layer stacked die devices such as those seen in high bandwidth memory," said Thomas Rodgers, senior director of market strategy at Zeiss Microscopy.

What hides after bonding?

Buried defects remain the hardest problem. Infrared metrology verifies pad alignment through the silicon. X-ray methods — CT, laminography and high-resolution XRDI — inspect the bond interface; 150 nm resolution has been demonstrated. "We can detect subsurface critical defects on patterned/metalized wafers with zero edge exclusion," said John Wall of Bruker JV UK. "Full wafer inspection can be performed at ~20wph."

For cracks and delamination, ultrasound leads. "Acoustic micro-imaging using ultrasound in the 200MHz range provides the highest resolution," said Nordson Test & Inspection's Bryan Schackmuth. Ultrasound does not cross air gaps down to about 0.1 µm thick, so delaminations of 5 to 10 µm laterally are detectable. But resolution lags pitch: a 165 MHz transducer resolves 12 µm defects accurately, while a 5 µm void can be detected but not measured. Nordson is developing higher-frequency transducers to close that gap.

No single technique combines the resolution, sensitivity, wafer coverage and throughput to catch every yield-critical defect. As pitches scale below 5 µm, vendors of faster and more complementary metrology — not just bonding equipment — will decide how quickly true 3D integration reaches high-volume manufacturing.