Which Passing Chips Deserve Another Look Before They Ship

A chip can pass wafer sort, survive assembly, clear final test, and still fail in the field — and test engineers increasingly can tell which passing parts carry that hidden risk. That's the core problem now confronting manufacturers as advanced nodes and multi-die packages make marginal behavior both harder to catch and more expensive to miss.

"The cost of test and the amount of test is exploding, and the ability to test before system-level test is a challenge," said Kimon Michaels, executive vice president of products and solutions, director, and co-founder of PDF Solutions. "But of course, one of the big challenges is how much of your supply chain is at risk at that point, or the amount of product that you're throwing away if it fails at that point."

The economics are brutal on both sides. Extra patterns eat tester time. Burn-in ties up equipment. A packaged device may need another mechanical insertion. Rejecting every statistical outlier throws away good silicon. But the alternative is worse. "Nothing is more expensive than a field failure," said Michaels, adding that advanced technologies are in some respects even more sensitive to reliability failures.

Why passing doesn't mean reliable

Manufacturing tests only approximate real operating conditions. Voltage, temperature, timing, and workload are controllable on the tester, but the interactions inside an assembled system are far harder to reproduce.

"Individual dies can pass wafer sort and final test, and then behave differently once the dies, memory devices, interconnects, firmware, and software are all working together," said Eli Roth, smart manufacturing product manager at Teradyne. "We're very good at finding hard failures. What's much harder is finding devices that meet spec but are operating close to a reliability boundary."

What do device-level models reveal?

Conventional production testing leans on defined limits, with guard-bands for measurement uncertainty and operating variation. Statistical analysis can flag devices near those limits or behaving differently from their wafer neighbors. But a chip can pass every test while showing an unusual relationship among its measurements.

Device-specific models close that gap. By comparing internal parametric measurements against expected behavior for a particular device, engineers catch inconsistencies that population-based statistics miss. Process and timing signatures predict how a chip should behave; discrepancies between predicted and measured performance become the signal. Design-related margin limits show up consistently across a product population. Material problems don't.

"Material-induced variability behaves differently. It is often localized, asymmetric, or statistically scattered," said Nir Sever, senior director of business development at proteanTecs. "Only a subset of devices, wafers, or regions on a die may show accelerated drift. The degradation slope may diverge from the population over time."

Localized or accelerating changes can point to an emerging physical weakness. The catch: an anomaly isn't proof of a defect. And the models themselves decay.

"Data is not static," said Michaels. "It drifts. It's physics-based. There are changes to the process, and you have to be cognizant of that in how you retrain, how you monitor, etc."

How inspection explains marginal behavior

Some latent defects never produce a consistent electrical failure. A weakened interconnect may conduct fine at room temperature and go unstable under thermal or mechanical stress. Advanced packages make this worse: partial non-wetting, micro-bump voids, delamination, and warpage may not cause an immediate failure at all.

"Voiding and non-wetting may weaken an interconnect without causing an immediate open," said Chris Rand, principal technical engineer at Nordson Test & Inspection. "Variation in bump height, solder volume, or interconnect geometry can shift resistance or create continuity that changes under load, temperature, or handling."

X-ray and acoustic inspection can supply physical evidence of a suspected interconnect problem, while electrical measurements establish whether the irregularity actually affects behavior. Neither technique gives a complete diagnosis alone. Correlating the two narrows the possible failure mechanisms and helps engineers pick a stress condition more likely to expose the weakness.

Cross-insertion comparison adds another clue. A chip may pass at every stage while its electrical characteristics slowly shift — a trend individual pass/fail decisions miss.

"An unexplained drift is not a healthy sign," said Greg Prewitt, director of Exensio Solutions at PDF Solutions. "If a device just changes, and you don't think it's a problem with the test setup, it requires more scrutiny."

Before chasing that drift, engineers must rule out temperature, calibration, contact resistance, or instrument configuration. Otherwise they risk pursuing a healthy device while missing a fault in the measurement path.

Which test comes next?

Once evidence points to a credible failure mechanism, the question becomes which additional test can actually expose it. The options aren't interchangeable:

• Suspicious timing may call for characterization at a different voltage or temperature.
• An interconnect concern may need electrical or thermal stress.
• A reliability-risk signature may justify burn-in.

Repeating the original test under the same conditions adds little if that test was never sensitive to the defect.

Burn-in is the toughest call. Elevated temperature and voltage accelerate certain mechanisms, but the process consumes equipment time, power, and capacity — and the stress itself can damage reliability. That makes blanket burn-in hard to justify when only a small fraction of passing devices are at risk.

"People are burning in large fractions of their inventory, or nearly all of it, which is expensive and can cause damage by itself," said Michaels. "But a fairly broad model can learn the insights as to what multi-dimensional part of your process-based plus your test state predicts, and what the sweet spot is where you can skip it and focus your resources on the more marginal parts where you have concern."

Predictive burn-in uses manufacturing history and test data to identify devices most likely to benefit from stress screening. Adaptive test takes a related route, using wafer- and die-level results to shape post-assembly testing — provided the manufacturer can preserve device identity across operations.

"We have established a kind of cloud infrastructure that is fetching data from the different test insertions and reusing the data collected at earlier test insertions to optimize the die matching inside advanced packaging, the test conditions and consequently the yield for the following test insertions," said Fabio Pizza, test technology director at Advantest. "You can have a kind of adaptive test to make sure that when you test the device after assembly, you are using the right limits and even the right pattern."

Changing limits or patterns within an existing insertion costs less overhead than routing a packaged device through another operation. And as more value piles into each device, the math shifts.

"When you look at the economics, test costs are dwarfed by scrap costs once you start packaging these devices together," said Teradyne's Roth.

Why retesting creates its own uncertainty

Retesting sounds like cheap insurance. It isn't. Production test runs through physical interfaces, and packaged devices get pressed into sockets with substantial force across hundreds or thousands of terminals. Contacts wear, surfaces contaminate, and small seating variations change resistance. A second insertion may not reproduce the first even with an identical test program.

"Every time you put that part into the socket, there's risk involved," said Jack Lewis, chief technologist at Modus Test. "So retest is a problem. You don't want to be retesting. Test times are long."

A pass after an earlier fail is especially ambiguous — healthy device with a contact-induced false failure, or intermittent defect that simply stayed quiet the second time? Changing the bin without keeping the history throws away exactly the information needed to tell those cases apart.

Advantest's Pizza said customers also want dedicated measurements to monitor whether any parameter of the complete test cell is deviating — any resource in the tester, load board, probe card, or thermal control system drifting toward its limit and potentially creating marginalities when testing such devices. That monitoring helps separate changes in the measurement environment from changes in the silicon.

When does decision latency kill screening?

Even a good model fails operationally if its answer arrives too late. Some production test operations complete in fractions of a second, and an analysis finished after the lot moves on may help future process work without changing the disposition of the parts that generated the data.

Roth described an IDM customer whose test infrastructure deliberately deferred building test data files until the tester had idle time. Throughput held, but response suffered.

"In extreme cases, STDF files aren't built until the end of a lot," said Roth. "So if something goes wrong on an early wafer, we're not collecting or presenting that data in time for anyone to act on it. Historically, that's been the trade-off in the push for throughput."

New designs compound the problem. Complex devices generate enormous measurement data, but engineers may have little historical information to judge what's unusual.

"Being able to accurately, empirically assess the data and find out what's anomalous and what's not is by no means an easy task," said Brent Bullock, test technology director at Advantest. "Engineers may not have reliable historical data for comparison, particularly when testing a new chip design or moving to a different architecture."

Engineers also need a feedback loop: why a device was flagged, what evidence triggered the decision, what the extra test found, whether the result supported the original risk assessment. Without it, screening rules accumulate that are expensive to maintain and hard to justify.

How much uncertainty will the market accept?

The final call comes down to what manufacturers can establish about a device and how much residual risk they'll accept. A risk score may justify further characterization or closer monitoring — not automatic scrapping. The calculation varies by market: high-volume consumer suppliers will balance test cost against risk differently than those serving automotive or industrial customers. And as more data becomes available per device, the hard question shifts from whether a manufacturer can take another measurement to whether that measurement is likely to change the outcome. The better they get at that judgment, the less extra testing they may ultimately need.