Test Intensity Has Doubled as AI Chips Outpace Test Strategies

Test intensity for AI chips has at least doubled over the AI era, driven by assemblies that can be worth $30,000 to $50,000 once they hit rack assembly. "We cannot throw away $30,000 because of a defective chiplet," said Jeorge Hutarte, senior director of product marketing in the Semiconductor Test group at Teradyne.

That is the blunt commercial reality behind a structural shift in semiconductor manufacturing. AI workloads are changing faster than chips can be designed, manufactured and tested, forcing chipmakers to rethink what to test, when to test it, and what to monitor once silicon is in the field.

Until recently, test targets and the timing of test insertions were set by fab processes and the laws of physics, with deterministic, quantifiable results. Since generative AI rolled out and data centers exploded, the gap between new algorithms and deployed silicon has widened into a scheduling mismatch. It took slightly more than two years from the introduction of ChatGPT in November 2022 to widespread commercial adoption of agentic AI — roughly the time it takes to design, verify, validate, fabricate, package and integrate a chip.

What changed at the package level?

An increasing number of data-center processors, and many at the edge, are multi-die assemblies. They take longer to design, manufacture, package and assemble — and the workloads they target often change before the chips leave final test. Each additional test insertion generates more data, much of it siloed across companies and facilities.

"It's a huge challenge," said Scott Segura, vice president of sales at Advantest. "People are starting to put more active components into the substrate, and moving things closer to each other, so it's turning into more test insertions. What shifts left? What shifts right?" Functional testing is now moving into substrate testing, he noted, and known good dies must be able to handle 3 kilowatts at the die level. Silicon photonics already has five test insertions, he added.

The transition from round wafers to rectangular panels — packing as many dies as possible onto a 310 × 310mm panel — will require entirely new equipment and processes. Packaging and assembly, once done in one location, is now split between fabs and OSATs. That creates friction over who sees what data, and when.

"Test insertions typically are done at different locations," Hutarte said. A fab may run wafer sort and singulated die probe with its own data workflows; the OSAT then assembles a compute die plus a stack of HBMs and other chiplets on an interposer, with a different test program and data environment. "They don't necessarily talk to the previous test insertion data. And unfortunately in the fabless world, people don't share data unless the customer owns everything."

Why do chips arrive outdated?

Even if the design cycle shrank from today's 18 to 24 months to 6 months — a stated goal of some large chipmakers — new training and inference models would still roll out faster than working silicon. "We have customers now that will tape out chips, run their models on them... and they'll end up not going to market with them," Segura said. They may change memory stacking, core count or cache. "Even our customers sometimes guess wrong." A chiplet design planned for 256 cores may only need 192 by the time silicon returns.

To cut losses, some companies now insert a wafer-level burn-in stage between wafer sort and singulated die, accelerating infant mortality before committing a die to the interposer stack. Every wrong screening in the AI accelerator world translates to thousands of dollars of loss, Hutarte said — unlike the mobility era.

Can data silos be broken?

The data problem spans technical and organizational walls. "Not only are there more tools, but they're all generating more data — and pretty rich modes of data with lots of images," said Jim Schiely, chief of staff for Calibre Semiconductor R&D at Siemens EDA. His proposed fix: "AI to the rescue" — AI tools can stitch digital threads together across departments even with different data models.

Kimon Michaels, co-founder and EVP at PDF Solutions, said the industry needs analytics networked across the supply chain, with data sharing that protects IP. "We're not there yet as an industry for sure," he said. Rahima Mohammed, distinguished engineer at Vinci, added that engineers must now reason from the nanometer level up to the package level, tracking self-heating, dielectric degradation and workload scheduling to keep AI hardware alive longer.

Until AI settles into a use pattern that isn't uprooted every month or so, test will remain a unique, tailored and increasingly costly process for every design — and chipmakers will keep facing hard choices about how much customization competitive survival actually requires.