Microsoft Commits Billions To AMD Helios Racks For Azure Inference
Microsoft will deploy AMD's Helios rack across Azure, anchored by hundreds of thousands of MI455X GPUs running frontier-model inference. Deal estimates range from $5B to $10B.
- By
- Nathan Brooks
- Filed
- Channel
- AI & Compute
- Read
- 3 min read
The headline figure is 2.9 exaflops at FP4 precision from a single Helios rack. That is the AMD reference design Microsoft has chosen as the building block for a multi-billion-dollar Azure inference fleet, with the software stack, CPU, GPU, and DPU all coming from AMD.
Industry estimates put the deal between $5 billion and $10 billion, anchored by hundreds of thousands of Altair MI455X GPUs. Neither Microsoft nor AMD will confirm the dollar value, though both companies fronted the announcement ahead of AMD's Advancing AI 2026 event in Silicon Valley. AMD is the only vendor applying direct pressure on Nvidia in the two segments where Nvidia is minting the most revenue.
What does the Helios rack contain?
The double-wide chassis holds 18 compute trays, each tray carrying one Venice Epyc 9006 CPU and four MI455X GPUs. That arrangement produces 4,600 Zen 6 cores across the rack and 72 GPUs total, with 18,000 GPU compute units and 256 cores per Venice processor.
Memory comes from 31 TB of HBM4 stacked across the GPUs, and the Pensando DPUs push 43 TB/sec of aggregate bandwidth. The DPUs remain programmable through the P4 language, a feature Microsoft has leaned on heavily since its initial Pensando deployment. Microsoft has arguably been the dominant deployer of Pensando silicon to date.
What runs on the cluster?
Inference for Azure-hosted frontier models. The workloads do not include training, which keeps the cluster squarely in the deployment tier rather than the model-building tier. The narrow targeting matters because inference and training fleets place different demands on HBM bandwidth and inter-GPU latency.
Microsoft is also rolling out two CPU-only Azure instances built around Venice Epyc. HDv2 will handle agentic AI workloads and their data pipelines, while HXv2 will serve electronic design automation for chip design. The HXv2 instances likely carry more cores than HDv2, though Microsoft has not specified the count.
The company is also migrating its Azure Boost acceleration software onto Pensando DPUs. Microsoft had built its own DPU for the initial Azure Boost deployment in November 2024 and is now porting its homegrown networking and storage virtualization to P4 routines running on Pensando silicon.
Which fabric ties the rack together?
Scale-out networking is almost certainly Ethernet, with Arista Networks a probable switch supplier. Scale-up networking inside the rack, the fabric stitching the HBM pools of the MI455X GPUs together, is murkier.
Microsoft and Meta Platforms back ESUN, a coherent memory fabric positioned as an alternative to Nvidia's NVLink-NVSwitch combination. AMD and partners launched UALink in May 2024 as a second alternative. Microsoft may start with ESUN running on low-latency Ethernet switches in its initial Helios racks and migrate to UALink switches further down the road, but the company has not committed publicly to either path.
What does this mean for the Nvidia-AMD split?
HBM allocation drives the GPU mix. If Nvidia controls 80 percent of Microsoft's HBM supply, Nvidia ships 80 percent of the accelerators. The math is that direct.
The current split is probably 70 to 75 percent Nvidia and 25 to 30 percent AMD, and AMD's share of the AI training and inference pie is climbing. If AMD's growing footprint does not bring proportional HBM allocations, expect antitrust complaints over restraint of trade to multiply quickly.
AMD's share of Microsoft's AI silicon is growing, and HBM allocation has to follow or face legal scrutiny. The Advancing AI event in Silicon Valley this week should clarify which networking fabric Microsoft picks for the scale-up tier, and whether AMD's rack pitch is winning converts beyond Azure.
Source: The Next Platform
More from Nathan Brooks
Show full bio
Senior reporter covering people, launches and day-to-day practice in Semiconductors, chip manufacturing, hardware, AI compute at Chip Dispatch.
358 articles
Related articles
amd-outlines-venice-cpus-mi455x-gpus-and-helios-rack-roadmap-383b3463
AMD Outlines Venice CPUs, MI455X GPUs, and Helios Rack Roadmap
tencent-leases-100-000-chips-from-oracle-to-scale-ai-compute-8c8cbffb
Tencent Leases 100,000 Chips From Oracle To Scale AI Compute
amd-crosses-1-trillion-in-market-value-4e5ef02c
AMD Crosses $1 Trillion in Market Value
amazon-seeks-to-move-8b-of-nvidia-ai-chips-off-its-books-227e78d5
Amazon Seeks to Move $8B of Nvidia AI Chips Off Its Books


