Nvidia’s NVHBM Sidesteps JEDEC in the HBM4 Stack

By Grace Kim

Morgan Stanley estimates Nvidia will purchase 37% of the global HBM supply in 2027. That expected demand gives Nvidia unusual leverage over Samsung, SK Hynix and Micron, the only three HBM manufacturing suppliers.

Nvidia says its NVHBM interface delivers “up to 30 percent greater memory bandwidth” and “15 percent lower HBM power consumption” than standard HBM4E. The company also claims the design frees up to 25 percent more area on the GPU compute die. These figures remain company claims rather than independently reported benchmarks.

The custom interface came with Nvidia’s August NVLink Fusion announcement. It moves the memory-controller function from the GPU into the HBM base die. That relocation opens space for more AI-processing GPU cores. It also lets Nvidia tailor the physical path between GPU and memory.

What changes inside a GPU package?

HBM is interposer-connected stacked memory used with GPUs. It bypasses the capacity and bandwidth limits of x86 socket-connected DRAM. The Joint Electron Device Engineering Council (JEDEC) published its first HBM standard, JESD235, in 2013. JEDEC restricted access to the specification.

Samsung, SK Hynix and Micron built chips compliant with that standard. Nvidia, its system-building partners and other GPU builders bought most of them. Nvidia now modifies the controller arrangement rather than accepting the JEDEC design unchanged.

Conventional HBM uses a wide physical interface with many pins. The memory stack connects through an interposer to a GPU containing the memory controller. NVHBM uses a narrower, custom PHY interface. Its controller sits on the base die, outside the GPU. The claimed result is more GPU-core space and more HBM bandwidth, allowing Nvidia to tune both halves of the package around its own accelerator design requirements.

Why can Nvidia alter the interface?

NVHBM remains Nvidia-specific. It is not a JEDEC industry standard. Yet it already has the commercial structure of a de facto standard. Nvidia is the dominant HBM buyer, the supplier base contains only three manufacturers, and all three support Nvidia’s approach.

The 37% share is an analyst forecast, not a disclosed Nvidia purchase commitment, but it indicates the scale of demand Nvidia could direct toward the custom interface and its suppliers. Supporting the market’s largest buyer may matter more to Samsung, SK Hynix and Micron than preserving one committee’s rules.

Nvidia has also dictated the foundry process used for its HBM work: TSMC’s 3nm. Reuters reported Samsung will accede to that request. South Korea’s Seoul Economic Daily said Samsung would nevertheless build JEDEC-standard HBM in-house for other customers. That preserves Samsung’s route to the wider HBM market.

Amazon’s Annapurna Labs unit supports NVHBM as an Nvidia NVLink partner. The support adds an independent ecosystem participant to Nvidia’s custom memory path.

What can JEDEC do now?

JEDEC has issued no public comment about NVHBM. Its possible responses remain open. Three courses are apparent from the standard-setting conflict:

• Accept Nvidia’s expanded role by restricting HBM specification work to the stack above the base memory-controller die.
• Continue the existing JEDEC process with Nvidia absent.
• Move toward NVHBM by specifying a base controller die with narrower, faster physical channels, building on reduced-pin-count work already under way.

When JEDEC announced HBM4 in April 2024, HBM subcommittee chair Barry Wagner was Nvidia’s director of technical marketing. His continued chairmanship may now be untenable. Nvidia is challenging the scope of a committee that its own executive still leads.

The decisive contest now concerns standard-setting power. If Nvidia converts its projected 37% supply share into broad supplier adoption, NVHBM could become the market’s operating specification and leave JEDEC with a narrower role.