By Sophie Lindqvist

NXP has integrated a 10BASE-T1S single-pair Ethernet PHY directly into a 240-MHz Cortex-M33 microcontroller, the MCX A5. The device pairs a 10/100 Ethernet MAC with the PHY on one die. It serves as a node on a 25-meter multidrop IP-based Ethernet segment.

The MCX A5 sits among the first microcontrollers to ship with the 10BASE-T1S PHY built in. Prior designs typically relied on an external transceiver chip. NXP frames the integration as a reduction in board area and bill-of-materials cost for industrial sensor nodes.

What does the integrated 10BASE-T1S PHY actually deliver?

Single-pair Ethernet (SPE) replaces legacy fieldbus and serial links across factory and vehicle networks. The 10BASE-T1S variant carries IP traffic over a single twisted pair. It supports time-sensitive networking (TSN) and MACSEC security at the link layer.

Justin Mortimer, senior director of product marketing at NXP, characterized the integrated PHY in a briefing as the defining feature for multidrop sensor segments in industrial, commercial, and automotive networks. NXP cites flexibility and performance gains over serial bus solutions.

Power delivery remains optional. Power over Data Line (PoDL) requires additional external hardware, unlike the chip itself. PoDL shares concepts with Power over Ethernet (PoE), but the standards differ in topology and cable requirements. Many sensor nodes draw from local supplies instead. A gateway typically bridges the multidrop segment to a standard Ethernet switch.

How does the security block hold up?

The security enclave centers on NXP's EdgeLock technology. It employs post-quantum cryptography (PQC), a hardware root of trust, secure boot, secure debugging, and tamper and intrusion detection. NXP describes PQC as preparation for future regulatory mandates in the part's target applications.

Memory comprises a dual-bank, 2 MB on-chip flash array. External serial memory attaches through a FlexSPI interface with caching hardware and execute-in-place (XIP) support. The combination lets code run directly from external flash without copying into SRAM first.

What peripherals accompany the network engine?

Touch-sensing (TSI) and FlexIO interfaces provide human-machine interface (HMI) support. Two 16-bit ADCs and two DACs sit alongside a built-in temperature sensor and voltage reference (VREF). The peripheral mix targets sensor and control subsystems across the part's industrial and automotive use cases.

Communications include multiple I2C, I3C, SPI, UARTs, and dual CAN FD ports. A real-time clock (RTC) and a micro-tick timer handle scheduling. The peripheral set supports sensor aggregation, motor control, and HMI applications tied together via a single 10BASE-T1S network.

What remains undisclosed?

NXP has not disclosed pricing, sampling dates, or volume figures for the MCX A5. The company also did not name the process node or foundry partner. Those gaps matter for any direct cost comparison against competing parts.

Caveats apply to the integrated-PHY claim itself. The 10BASE-T1S standard supports multidrop runs at varying distances depending on cable quality and node count. NXP specifies 25 meters for the basic segment. Larger plants will require repeaters or gateways, adding cost and complexity.

Competing microcontrollers with external PHYs remain widely available from multiple vendors. External transceivers add board area and a second point of failure on the network interface. Adoption of the MCX A5 will hinge on PoDL ecosystem maturity and gateway availability from third parties.

NXP's broader roadmap will shape whether integrated 10BASE-T1S becomes the default for sensor-class microcontrollers. Competing silicon vendors could follow with their own integrated parts in subsequent product cycles. Pricing remains the central unknown for design wins across the part's target segments.