Synopsys and TSMC have broadened their long-running collaboration to support the design of next-generation artificial intelligence systems, extending a partnership that already spans EDA tool certification on advanced TSMC process nodes, IP development, and reference flows.

The announcement, reported by New Electronics, signals that both companies intend to tighten the integration between Synopsys' design software and IP portfolio and TSMC's leading-edge manufacturing technologies as AI workloads push chip architectures toward larger die sizes, higher power envelopes and greater packaging complexity. Neither company disclosed new financial terms attached to the expanded arrangement, and no new capacity or volume commitments form part of the agreement, according to the report.

The partnership matters because AI silicon sits at the intersection of the industry's most demanding design problems. Training and inference accelerators increasingly combine reticle-scale logic dies, high-bandwidth memory stacks and chiplet-based interconnects in advanced packaging such as TSMC's CoWoS and InFO family. Designing these systems requires EDA tools, process design kits and silicon-proven IP that are validated together well before a customer commits to a multi-year, multi-billion-dollar tape-out schedule.

Synopsys and TSMC have collaborated for decades across these layers. Synopsys tools are certified on TSMC's most advanced nodes — including the N3 family and the N2 nanosheet-gate technology that TSMC has slated for high-volume manufacturing — and the two companies jointly develop reference methodologies that customers use to bring up designs on new processes. They also cooperate on interface IP, foundation IP and multi-die design flows, all of which have become central to AI system construction as single-die scaling slows and designers turn to disaggregated architectures.

The expanded collaboration follows a period of intense capital spending and roadmap acceleration across the AI supply chain. TSMC is pouring investment into advanced packaging capacity to serve AI accelerator demand, and its leading-edge nodes are booked heavily by designers of AI training silicon. For Synopsys, AI chips represent one of the fastest-growing segments for EDA licensing, since large accelerated-computing devices generate more design starts, more verification load and more IP content per project than conventional SoCs.

The report does not specify which process nodes, packaging technologies or product families the widened cooperation will cover, and no timeline for joint deliverables was announced. That leaves the commercial shape of the arrangement — whether it involves co-developed IP, dedicated design flows for a specific TSMC node or packaging option, or early access programs for AI-focused customers — undefined for now.

What the deal does confirm is strategic direction. Foundries and EDA vendors are moving closer together as AI system design collapses traditional boundaries between chip design, packaging and system integration. TSMC's customers increasingly need multi-die solutions that combine logic, memory and interconnect, and Synopsys has positioned its toolchain and IP around exactly that problem. A tighter alliance gives both companies a stronger claim on the next wave of AI design starts, which carry high engineering-services intensity and premium IP attach rates.

The competitive backdrop adds weight. AI accelerator programs at the largest hyperscalers and chip vendors compete for leading-edge capacity, and differentiation increasingly depends on how quickly a design team can move from architecture to silicon on a new node and packaging scheme. EDA-foundry partnerships that shorten that path — through pre-certified flows, silicon-proven IP and joint validation — directly affect time-to-revenue for the chipmakers and for TSMC's advanced-node utilization.

For Synopsys, the agreement reinforces its position against rivals in EDA, where tool certification on the industry's most advanced foundry process is table stakes for winning AI-era design activity. For TSMC, deepening ties with a leading EDA and IP supplier supports its strategy of making its leading-edge nodes and packaging technologies the default platform for AI silicon.

Both companies have framed AI as both a demand driver and an engineering opportunity: AI chips are among the most complex devices ever designed, while AI-assisted design tools promise productivity gains in verification, physical implementation and layout. The expanded cooperation is positioned to serve both sides of that equation, though the announcement itself did not detail specific AI-driven tooling initiatives.

Industry attention will now turn to the practical outputs: joint reference flows for TSMC's next nodes, expanded multi-die design enablement, and IP availability aligned to the foundry's packaging roadmap. As AI accelerators continue to consume the bulk of leading-edge capacity and drive packaging investment across the supply chain, the depth of the Synopsys–TSMC alliance will shape how quickly the next generation of AI systems reaches volume production.