Synopsys has certified its electronic design automation flows for TSMC's A14 process node and has taped out a 64G UCIe die-to-die interconnect on both 2nm and 3nm technologies, moves that lock the EDA and IP supplier into TSMC's leading-edge roadmap before those nodes reach volume production.

The certification of Synopsys EDA flows for TSMC A14 — the foundry's 1.4nm-class node — extends a partnership that already covers N2 and N3 silicon. Alongside the flow certification, Synopsys confirmed silicon validation of its Universal Chiplet Interconnect Express (UCIe) IP running at 64 Gbps per lane, produced on both TSMC's 2nm and 3nm processes. UCIe has become the de facto standard for connecting chiplets within multi-die packages, and working silicon at 64G data rates on two leading nodes gives Synopsys a concrete proof point that designers can license rather than develop in-house.

The tape-outs position Synopsys to serve the two customer categories now driving leading-edge demand: AI accelerator developers assembling multi-chiplet packages and hyperscalers building custom silicon. Both groups rely heavily on die-to-die interconnects, high-bandwidth memory interfaces and PCI Express links to scale performance beyond what a single reticle-limited die can deliver.

Synopsys also highlighted progress on two additional interface IP families central to next-generation AI and data center systems. The company is developing PCI Express 7.0 IP, the generation that doubles per-lane bandwidth again for host-to-device connectivity, and HBM4 controller and PHY IP for the next step in high-bandwidth memory interfacing. HBM4 support matters commercially because memory bandwidth, not compute, increasingly gates AI accelerator performance, and every leading-edge AI chip design now pairs logic silicon with stacked HBM near-package memory.

The timing aligns with TSMC's node cadence. TSMC plans to ramp 2nm volume production in 2025, with A14 following later in the decade. By certifying EDA flows and validating IP this early — typically 18 to 36 months before a node reaches high-volume manufacturing — Synopsys removes a key adoption barrier: customers will not commit multi-hundred-million-dollar tape-outs to a node unless the full EDA-plus-IP toolchain is proven on it.

For Synopsys, the announcement strengthens the moat around its two-pronged business. The company sells both the design software used to build leading-edge chips and the pre-verified interface IP (UCIe, PCIe, HBM controllers, Ethernet and others) that shortens customer schedules. Certifications with TSMC effectively make Synopsys flows the default starting point for A14 designs, which in turn drives IP attach rates — a customer adopting a certified flow typically licenses multiple IP blocks alongside it.

The competitive context sharpens the stakes. Cadence maintains a parallel certification program with TSMC and has announced its own UCIe and HBM4 IP work, and Alphawave, Credo and Rambus compete aggressively in the serdes and memory-interface IP segment. Silicon-proven results on 2nm and 3nm give Synopsys a verifiable lead indicator in that race, since IP vendors compete heavily on demonstrated silicon rather than paper specifications.

The announcements also trace the industry's structural shift toward multi-die architectures. A 64G UCIe link validated across two nodes means designers can mix chiplets built on different processes — for example, compute logic on 2nm and I/O chiplets on a cheaper mature node — while maintaining a standard interconnect between them. That flexibility is the core economic argument for chiplet-based design, and interface IP vendors are the toll collectors on that transition.

Synopsys has not disclosed customer names, shipment volumes or licensing revenue tied to the new IP. PCIe 7.0 and HBM4 IP remain in development rather than broadly available, so near-term commercial impact will come first from the certified A14 and 2nm/3nm UCIe deliverables.

As TSMC ramps 2nm and drafts A14 customers, expect the race among Synopsys, Cadence and the specialist IP houses to shift to who can demonstrate the most silicon across the most nodes first — because in chiplet design, the interconnect IP wins the socket.