Cadence Design Systems has certified its digital full-flow, signoff and custom/analog tool flows for TSMC's A16 and A14 process technologies, anchoring an expanded collaboration announced September 23, 2026, that also covers silicon-proven IP for N3P and N2P and a demonstrated UALink solution in TSMC N3P.

The certification work targets the customers now pushing TSMC's most advanced nodes: designers of AI accelerators and high-performance computing silicon. According to the Cadence Newsroom announcement, the companies' joint work includes AI chip and three-dimensional integrated-circuit design flows spanning TSMC's N3, N2, A16 and A14 technologies. Analog, digital and signoff flows were separately certified for N2P, extending coverage of TSMC's second-generation 2-nanometer-class family.

For Cadence, tool certification on a leading-edge node is a commercial gate. Fabless design teams standardize on EDA flows only after the foundry validates them against its process design kits and design-rule decks. Certification for A14 — a node TSMC has positioned beyond A16 in its roadmap — signals that Cadence's digital, signoff and custom/analog tools will be ready when the process reaches early design engagements, keeping the company aligned with Synopsys in the race to support each successive node.

The packaging side of the announcement is equally concrete. Cadence said its solutions now support TSMC SoW-X designs carrying hundreds of chiplets and millions of bumps. SoW-X is TSMC's system-on-wafer approach, in which multiple chiplets are integrated on a carrier wafer rather than assembled as discrete packages on a substrate. Supporting designs at that scale — the bump counts run into seven figures — places heavy demands on physical verification, parasitic extraction and interconnect analysis, and Cadence is positioning its flows to handle them. This matters commercially because AI-training and hyperscale-computing customers are the ones adopting wafer-scale and 3D-IC integration fastest, and EDA vendors that certify early for those packaging technologies capture the associated tool and IP revenue.

The UALink element adds an interconnect dimension. Cadence demonstrated a UALink solution in TSMC N3P and introduced silicon-proven IP for both N3P and N2P. UALink is the scale-up interconnect standard backed by a consortium of AI accelerator and hyperscale companies as an open alternative for chip-to-chip links in large AI systems. Silicon-proven IP — libraries and interface cores that have already been fabricated on the target process — shortens customer design cycles and reduces respin risk, and Cadence describes its UALink IP as industry-leading in silicon-proven maturity on TSMC's advanced processes. Foundry-certified IP at a leading node is a sticky product: customers who license it typically bundle adjacent tool and library purchases.

A second announcement, dated September 15, 2026, extends Cadence's IP business into automotive audio. The company's Tensilica IP Group worked with Analog Devices on the next generation of SHARC automotive audio processors. According to Business Wire, the new SHARC-FX processor core delivers five times the performance of the previous-generation SHARC+ core used in Analog Devices' ADSP-SC59x family, and the platform targets automotive audio, voice and AI workloads. Automotive DSPs carry longer design-in cycles and stricter qualification requirements than consumer silicon, so a design win with Analog Devices gives Cadence a multi-generation revenue stream in a segment where switching costs are high.

Taken together, the two announcements show Cadence pressing on three fronts at once: leading-edge digital certification at A16 and A14, advanced packaging and 3D-IC support for SoW-X-scale designs, and silicon-proven IP spanning UALink interconnect and automotive DSP cores. If TSMC's A14 timeline holds and wafer-scale AI designs reach volume production, the certified flows and IP announced this week should translate into design starts — and Cadence will be measuring the payoff in license revenue as those chips move from tape-out to silicon.