Cadence Design Systems has secured tool certification for TSMC's A14 process, completing a four-node sweep that now spans N3, N2, A16 and A14 and opens a fully certified path to advanced AI and HPC silicon.

The certification, dated September 29, 2026, also extends to A16 and to the N2P variant, with each node receiving coverage across the digital, signoff and custom/analog tool families. Cadence demonstrated a UALink-based solution on TSMC's N3P process and introduced silicon-proven IP for both N3P and N2P.

What tools did Cadence certify for A14 and A16?

The digital full flow, signoff flow and custom/analog flow now run on both A14 and A16. Cadence's digital stack combines the Innovus Implementation System, the Genus synthesis solution, the Cerebrus Intelligent Chip Explorer for design-technology co-optimization, and signoff tools including Tempus, Voltus, Quantus, Pegasus, EMX and Liberate.

For analog and mixed-signal work, Virtuoso Studio provides design-rule-correct layout generation and automated design migration. Cadence states the Virtuoso flow can cut design iterations by up to 2.5X and lift first-pass success on AI, HPC and mobile system-on-chips. In short, every major Cadence tool family now has a certified entry point at the 1.4 nm and 1.6 nm classes.

Which IP blocks have taped out, and which are next?

Cadence's UCIe-64G die-to-die IP has taped out on A14, and LPDDR6 is in development. Artisan Foundation IP and mixed-signal IP for A14, including standard cells, GPIO and memory compilers for HPC/AI and networking, are expected in the fourth quarter of 2026.

On N2P, DDR5, LPDDR5 and PCIe 6.0 IP have already taped out, while PCIe 3.0 IP is set to tape out in Q4 2026. UCIe-64G silicon on N2P is undergoing testing, and the same block has been characterized on N3P. Cadence's broader HPC and AI portfolio covers HBM4 and HBM4E, LPDDR6 and LPDDR5X, DDR5-MRDIMM, PCIe 7.0, and UCIe 64G.

How does the 3D-IC and packaging story fit in?

Cadence has enabled its tools for TSMC's System-on-Wafer-X (SoW-X) full design flow, which targets wafer-scale systems containing hundreds of chiplets and millions of bumps. The flow supports 5X reticle-size CoWoS-L-style advanced packages, alongside SoIC, eDTC, MIMCap, integrated voltage regulators, HBM logic base dies and substrates.

The Integrity 3D-IC platform handles system planning and assembly, while a pre-simulation-driven die-to-die auto-routing flow has been certified with the Allegro Substrate Router and OmniRoute Advanced Interconnect Router. The router derives signal-integrity-optimized strategies across CoWoS architectures while meeting UCIe requirements. Cadence is also enabling TSMC-COUPE, the Compact Universal Photonic Engine, by pairing it with 224G SerDes IP aligned to UALink, ESUN, UltraEthernet and co-packaged optics ecosystems.

Who is using the flows today?

Global Unichip Corp. (GUC) is running Cadence solutions to develop custom silicon for AI accelerators and hyperscale systems on TSMC's advanced nodes. According to GUC, Cadence-driven automation helps reduce schedule risk on engagements that involve new process technologies, and optimized execution is becoming more important as designs move to N3P and N2P, particularly for early-adopter programs with tight schedules.

Why does the certification pattern matter commercially?

Certification is the gating step that lets a fabless customer commit a tape-out to a foundry process. By clearing A14, A16, N2P and N3P in one release window, Cadence positions itself as a default EDA entry point for any team building AI accelerators, HPC SoCs or chiplet-based systems on TSMC's most advanced processes. The breadth also matters for TSMC, which uses a wide certified-IP footprint to lower the friction of moving customers from N3 to N2 to A16 and into A14.

Looking ahead, with A14 IP still in flight and PCIe 3.0 plus Artisan Foundation IP both slated for Q4 2026 tape-outs, the volume of Cadence-driven designs on TSMC's leading-edge processes should grow sharply as AI and HPC customers transition from qualification runs to production silicon.