Panmnesia and Meta have validated silicon for a proposed CXL-based datacenter architecture that places up to 960 accelerators in a single coherence domain, an eightfold jump over Nvidia's GB200 NVL72 rack-scale system.

The joint proposal appears in Nature Reviews Electrical Engineering and treats the AI datacenter as one tightly-coupled processing resource rather than a collection of loosely-coordinated servers. The authors liken the target design to a single chip with cores, memory, and links placed for uniform path lengths in one coherence domain. As AI workloads spread across more devices, control and timing must extend beyond the rack.

Myoungsoo Jung, CEO of Panmnesia, framed the work as a roadmap toward treating AI infrastructure as one coherent system.

"As AI systems continue to scale, the ability to connect large numbers of accelerators and memory devices quickly and efficiently is becoming just as important as the performance of individual accelerators," he said. "This research outlines a direction for next-generation AI infrastructure, where CXL enables the entire datacenter to operate as a single computing system."

Why does the current design fall short?

Panmnesia points to heavy-tailed latency distributions in today's datacenters, with 99th-percentile round-trip latency running roughly five times the median. Accelerators inside a rack connect through fast scale-up links, the company notes, while connections that leave the rack rely on slower scale-out networks. The tail, rather than any single device, holds the job back, and the more devices that join, the worse it gets.

How does the proposed design differ from Nvidia's rack?

In the GB200 NVL72, one CPU pairs with two accelerators over NVLink-C2C, with the rack interior tied by NVLink and racks connected through Ethernet or InfiniBand. The Panmnesia–Meta scheme substitutes extended CXL, stretching cache coherence across racks of accelerators and exceeding the device count supported by both the GB200 NVL72 and the emerging UALink alternative.

Claimed gains over the Nvidia rack:

• Accelerators coordinated by a single CPU rise from 2 to 16, an eightfold increase
• Up to 960 accelerators operate together in a single coherence domain
• Data access latency falls from the microsecond range to several hundred nanoseconds, roughly an order of magnitude lower
• The failure replacement unit shrinks from a whole server to a single device

Which hardware elements handle the routing problem?

Three dedicated components carry the load:

• High-fan-out non-blocking switch, which connects many devices at once and keeps path lengths uniform regardless of source
• Link acceleration unit (LAU), which moves repetitive protocol processing onto a dedicated hardware pipeline and bounds latency variation at each hop
• Fabric controller, a combined CXL and PCIe controller that applies the same ordering policy across the entire system

The fabric controller and the LAU have completed silicon validation. The fabric switch has been fabricated as a physical chip, with pre-release silicon now reaching partners. Validation in manufactured silicon is the more unusual milestone here, and Panmnesia points to it as evidence the architecture can survive contact with a foundry process.

How is the system structured?

The design groups CPUs, accelerators, memory, and switches by function into trays. Trays group into pods, and pods connect through a fabric, a regular tray–pod–fabric hierarchy that preserves fixed-hop, more consistent communication paths and timing. Resources are pooled by type rather than locked inside discrete servers, which the authors credit for the finer-grained replacement policy.

What sits ahead?

Panmnesia is preparing the core components for commercial supply. Future development will turn to optical interconnects for additional speed and scalability, a path consistent with the broader industry shift toward photonics at the rack and fabric level. The architecture faces its commercial test as the silicon moves from validation to production volumes and the latency claims meet independent benchmarking.