A nanoelectronic device built at the University of Cambridge switches at currents roughly one million times lower than some conventional oxide-based memristors, according to test results published in Science Advances on April 23, 2026. The team behind it claims the technology could cut energy use in AI hardware by up to 70%. That figure is a projection, not a measured system-level result, and the devices face a manufacturing obstacle before they can reach a production wafer.

The work targets a well-known cost driver in AI infrastructure. Conventional chips shuttle data between separate memory and processing units, and that movement consumes large amounts of electricity as AI deployment expands. Neuromorphic computing merges memory and processing in one place, the way biological neurons do, which removes the transfer cost entirely.

What did the researchers actually build?

The Cambridge group, led by Dr. Babak Bakhit of the Department of Materials Science and Metallurgy, engineered a modified hafnium oxide thin film that works as a memristor. Hafnium oxide is already familiar to the semiconductor industry as a high-k gate dielectric, which matters for any future integration path. The team added strontium and titanium and used a two-step growth process, creating small p-n junctions at the interfaces between layers.

The design departs from mainstream memristor practice. Most existing devices work by forming and breaking tiny conductive filaments inside metal oxides, a mechanism that behaves unpredictably and often demands high voltages. The Cambridge device instead changes resistance by adjusting the energy barrier at its interfaces, which the researchers say produces more reliable switching.

"Filamentary devices suffer from random behavior," Bakhit said. "But because our devices switch at the interface, they show outstanding uniformity from cycle to cycle and from device to device."

How strong are the measured results?

The laboratory data covers several separate metrics. The devices achieve hundreds of stable conductance levels, a prerequisite for analogue in-memory computing. They survived tens of thousands of switching cycles and held their programmed states for about a day. They also demonstrated spike-timing dependent plasticity, the biological learning rule by which neurons strengthen or weaken connections based on timing.

"These are the properties you need if you want hardware that can learn and adapt, rather than just store bits," Bakhit said.

The 70% energy saving claim rests on the architecture, not on a deployed accelerator. It follows from eliminating data movement, combined with switching currents measured at roughly a millionth of those in some conventional oxide memristors. No chip-scale system yet incorporates the devices.

The takeaway: the measured device-level numbers are strong and specific, but the headline energy figure remains a potential outcome of the architecture rather than a demonstrated result.

Why does the 700°C problem matter?

The current fabrication process requires temperatures of around 700°C, well above what standard semiconductor manufacturing tolerates for many process steps. That gap, not device performance, is the main barrier between this laboratory result and an industrial product.

"This is currently the main challenge in our device fabrication process," Bakhit said. "But we're now working on ways to bring the temperature down to make it more compatible with standard industry processes."

If the team succeeds, the devices could be integrated into practical chip-scale systems. "If we can reduce the temperature and put these devices onto a chip, it would be a major step forward," he said.

Cambridge Enterprise, the university's commercialization arm, has filed a patent application. The research received funding from the Swedish Research Council, the Royal Academy of Engineering, the Royal Society, and UK Research and Innovation.

How long did the development take?

The result followed nearly three years of failed experiments. Bakhit said progress accelerated when he changed the fabrication sequence, adding oxygen only after forming the first layer.

"I spent almost three years on this," he said. "There were a huge number of failures. But at the end of November, we saw the first really good results. It's still early days of course, but if we can solve the temperature issue, this technology could be game-changing because the energy consumption is so much lower and at the same time, the device performance is highly promising."

The journal paper, "HfO2-based memristive synapses with asymmetrically extended p-n heterointerfaces for highly energy-efficient neuromorphic hardware," lists twelve authors from Cambridge and collaborating institutions.

The next milestone to watch is thermal budget reduction: if Cambridge brings processing temperatures within standard fab limits, the path from discrete devices to integrated neuromorphic chips — and any real claim on that 70% saving — opens up.