A teardown of Intel's Panther Lake has given the industry its closest look yet at 18A, the process node that carries the weight of the company's turnaround plan — and the physical analysis confirms what many process engineers already suspected: TSMC still leads on transistor density.

Panther Lake is the first commercial product family built on Intel 18A, and teardown coverage from Notebookcheck drawing on the die analysis lays out the node's characteristics in detail. The significance is straightforward. Intel has staked its foundry ambitions and its own client-silicon roadmap on 18A delivering competitive power, performance and area against TSMC's leading-edge nodes. Every independent measurement of the first shipping 18A silicon therefore functions as a public checkpoint on that strategy.

The density verdict matters most. Intel has marketed 18A as the node that would return the company to process leadership, pairing RibbonFET gate-all-around transistors with PowerVia backside power delivery — two architectural changes TSMC has not yet shipped in high volume. The teardown-based comparison, however, finds TSMC's current leading-edge process still ahead on density. That is a commercial fact as much as a technical one. Density translates directly into die cost per transistor, and die cost determines how competitive Intel's products and foundry quotes can be against the world's dominant contract manufacturer.

The context sharpens the picture. Panther Lake arrives at a moment when Intel is splitting its foundry operations into an independent subsidiary and courting external customers, with US government backing under the CHIPS Act framework. 18A is the reference node for those pitches. If prospective foundry customers see independent teardowns confirming that 18A's density trails TSMC's best, Intel must sell them on something else — the power-delivery advantages of PowerVia, packaging integration, capacity availability outside Taiwan, or pricing.

The RibbonFET and PowerVia combination remains the genuine technical differentiator in Intel's story. Backside power delivery moves power rails beneath the transistor layer, freeing the interconnect layers above for signal routing, and Intel is first to ship it at scale in a client processor. TSMC plans its own backside power delivery with a future node generation rather than its current leading edge. Whether that first-mover advantage offsets TSMC's density lead is precisely the question teardown data now lets analysts quantify.

For Intel's client business, the stakes are equally concrete. Panther Lake carries the Core Ultra brand into its next generation and must compete against TSMC-fabricated silicon from AMD, Qualcomm and Apple on efficiency and performance per watt — the metrics where process technology shows up most visibly in laptop battery life and thin-and-light thermal budgets.

One teardown does not settle the foundry contest, and early production silicon typically lags later process maturity, when yields improve and density-optimized variants appear. But the first independent physical analysis of 18A in a shipping product sets the baseline: Intel has closed much of the gap and shipped genuinely novel transistor and power-delivery technology, while TSMC's density lead — and the cost structure that follows from it — remains intact. Future teardowns of subsequent 18A steppings and TSMC's next node will show whether that balance shifts.