Intel Built Nova Lake 8+16 Samples on 18A-P, Then Moved Compute Tiles to TSMC N2P

Intel produced its first Nova Lake 8+16 samples on its in-house 18A-P process, complete with backside power delivery, and then shifted the compute tiles for the product to TSMC's N2P node. That sequence, reported by Wccftech, is the sharpest signal yet of how Intel intends to split its next client platform between two leading-edge fabs.

The numbers matter before the narrative does. The sample in question is an 8+16 configuration — eight performance cores and sixteen efficiency cores, the signature layout of Intel's Nova Lake client family. The process behind the first silicon is 18A-P, the performance variant of Intel's 1.8-nanometer-class node with PowerVia backside power delivery. The eventual home of the compute tiles, according to the report, is TSMC's N2P, the enhanced second generation of TSMC's 2-nanometer family.

What did Intel actually prove on 18A-P?

The first-sample milestone answers a narrow but consequential question: can 18A-P carry a flagship client die through bring-up with backside power in place? By the report's account, it could, and did. Intel has staked its foundry credibility on 18A and PowerVia, and a working 8+16 part on that node is the kind of evidence that wafer-level test data alone cannot supply.

The irony is structural rather than subtle. Intel demonstrated the capability and then, for the compute tiles that ship in volume, chose TSMC. The report frames this as a deliberate allocation, not a rescue. A dual-source design of this sort gives Intel a hedge: 18A-P capacity stays reserved and de-risked, while TSMC's N2P absorbs the client volumes that launch schedules cannot gamble on.

Why hand the compute tiles to N2P?

Compute tiles are the most transistor-dense and yield-sensitive portion of any client processor. Placing them at TSMC on N2P implies Intel expects better density, yield, or schedule certainty there than its own ramp can guarantee for high-volume parts. I/O and other tiles, by the usual disaggregated-design logic, are less demanding and can sit on cheaper or older nodes.

For TSMC, the win extends a familiar pattern. Apple, Qualcomm, and MediaTek already anchor its N2 demand; an Intel client flagship on N2P would add a customer that was, until recently, cast as its chief process rival. For Intel Foundry, the calculus is blunt: a customer lost to the captive division, at least for this tile.

What remains unconfirmed?

Plenty. The report does not state volumes, launch dates, or pricing, and Intel has not, in the material cited, confirmed the final tile-to-node mapping for production silicon. First samples are engineering evidence, not a product plan. The distinction between what ran in a lab and what ships in a box is the whole story here.

The commercial picture, as it stands: Intel holds a working 18A-P demonstration in Nova Lake, while TSMC stands to take the volume compute business on N2P. Whether future client generations rebalance that split, or lock it in, will say more about 18A's maturity than any roadmap slide.