Physical AI Hits the Memory Wall: Why Compute Alone Won't Do

PwC's Strategy& projects the global physical AI market could reach approximately €430 billion by 2030, but the engineers building these systems say compute capacity is not the main obstacle. Memory bandwidth, power budgets, thermal limits and safety validation now set the real boundaries for robots, drones and autonomous vehicles.

"Physical AI systems are expanding beyond automotive to robotics and drones, and the bottlenecks for development of these applications cover the entire system," said Licinio Sousa, senior director of Interface IP for Automotive and Physical AI at Synopsys. "AI is expanding from the data center to the edge, and with machines such as robots, drones, and vehicles, all driven by the need for autonomy, privacy, personalization, faster response, and less reliance on the cloud."

Why does compute alone fall short?

The technical problems intertwine. Teams must increase memory capacity and bandwidth while cutting latency and power, stretch product lifespans, and verify safety. Fixing one problem often creates another elsewhere.

The answer, several executives argue, is a return to application-specific design. "We're basically going back to ASICs in the traditional sense of what ASICs were supposed to be — very application-specific, extremely optimized, versus more generic," said Michal Siwinski, executive vice president and chief product and marketing officer at Arteris. "The models are moving way faster."

Autonomous vehicles and robots share some stack elements, but robots face harder constraints. "An autonomous vehicle operates in a relatively structured road environment and draws power from a larger source — the vehicle battery," said Vasanthan Karunanithy, staff systems architect for Automotive at Micron Technology, speaking at the recent JEDEC Automotive Forum. "But when you look at robots, they operate in an unstructured 3D environment." A robot must manipulate objects, maintain balance, understand commands, and do it all on a limited power source.

Where does the silicon go?

Sousa said customers are already moving to purpose-built silicon for each class of machine, driven by vision-language-action (VLA) models. The variety of use cases makes a single monolithic architecture impractical, so Synopsys sees a transition to chiplets, where compute, AI, memory and I/O scale through a UCIe interface. Chiplets raise costs through custom packaging, thermal management and die-to-die communication; monolithic SoCs still win where power, size and cost are tight.

Intelligence placement is another tradeoff. "If you have intelligence distributed throughout a system, that makes it more complicated to update. Centralizing allows one point of over-the-air updates, easy to patch and fix, but it can create latency issues," said Yasmine King, corporate vice president and head of Automotive at Analog Devices. A car braking for a pedestrian cannot wait for a central processor.

How severe is the memory problem?

The industry now describes a "memory wall." "As memory footprint continues to grow, DRAM needs an ultra-fast interface, such as LPDDR6, to no longer be a bottleneck to processing," Sousa said. Raw bandwidth helps little if the workload is constrained by access patterns, cache capacity or memory-controller efficiency.

Sathish Balasubramanian, head of product for EDA AI & Solido at Siemens EDA, argues for right-sizing: "You don't need a 100-gallon tank in your Prius. You need a 10-gallon tank." Critical data stays in DRAM; the rest moves to flash or SRAM, with cache coherency across the path from DRAM to compute.

Lower precision helps too. Rob Fisher, senior director of product management at Imagination Technologies, noted that automotive players now market chips as combined automotive and robotics platforms, and that 4-, 6-, and 8-bit support benefits memory bandwidth and footprint at the embedded edge. Flash matters as well: faster storage bandwidth shortens model load times, so the same DRAM budget can support larger models in battery-powered systems without active cooling.

Could physical AI get its own memory type?

Steven Woo, fellow and distinguished inventor at Rambus, sees precedent. Phones once used binned DDR parts until the market justified LPDDR; data center demand produced HBM. "Physical AI has the potential to become a big enough market on its own, so that if the requirements vary enough, there could be another kind of memory," he said. Whether that happens depends on scale and consistency of demand across applications that differ widely in cost, temperature and endurance needs.

What about validation?

Before production, safety validation under rare conditions remains the hardest gate. "The validation loop that we need to bring physical AI into before we get into any production is paramount, and I would say is the most important thing we need to do," Balasubramanian said. Systems must survive power cuts, severed fiber links and degraded sensors with local intelligence near the sensor.

Owen Kent, co-founder of assistive robotics startup ATDev, frames the bar plainly: "Whatever hardware you use, whether it's custom or not, you have to be able to verify safety."

Balasubramanian's closing prescription is standards-based, low-power interfaces from sensor to actuator, citing the MIPI Camera Security Framework. Its CSE 2.0 specification supports data-integrity protection and optional encryption of CSI-2 camera data, giving end-to-end security from image sensor to SoC with tunable overhead. How quickly the €430 billion projection materializes will depend less on model capability than on whether memory, packaging and validation engineering can keep pace with it.