Siemens and TSMC have jointly developed an AI agent that automates the correction of design rule violations, one of the most time-consuming steps in turning a chip layout into a manufacturable design at TSMC's fabs.

The two companies announced the capability as an addition to Siemens' EDA portfolio, applying agentic AI to the design rule checking (DRC) and fix flow that every tapeout must clear before TSMC accepts a design for manufacturing.

Design rule fixes have long resisted automation. Traditional electronic design automation tools flag violations against a foundry's rule deck, but resolving them — resizing transistors, rerouting metal, adjusting spacing to satisfy a process node's physical constraints — has remained a largely manual task handled by layout engineers. As process nodes shrink and design rules multiply, the fix workload grows disproportionately, and foundries including TSMC have pushed customers and EDA vendors to shorten the iteration loops between layout teams and fab sign-off.

The Siemens-TSMC agent attacks that bottleneck directly. Rather than only reporting violations, it proposes and applies corrections, learning from TSMC's rule requirements so that fixes converge on sign-off-clean layouts with fewer manual iterations. For TSMC, the appeal is straightforward: cleaner, faster sign-off means more efficient use of its manufacturing capacity and smoother onboarding of designs across its process portfolio.

The collaboration fits a broader pattern in the EDA industry. Siemens EDA, the former Mentor Graphics that Siemens acquired in 2017, has invested heavily in AI-assisted design tools across place-and-route, verification and now physical verification sign-off. Rival Synopsys has made AI-driven design a centerpiece of its strategy, and Cadence has built out its own machine-learning toolchain. Agentic AI — systems that can plan and execute multi-step tasks rather than just infer or classify — represents the next competitive frontier, and Siemens and TSMC are claiming early ground in applying it to physical verification.

For chip designers, the commercial stakes are real. Physical verification and sign-off iterations routinely consume weeks at advanced nodes, and every deferred tapeout slot at TSMC carries opportunity cost in a market where leading-edge capacity remains tightly allocated. An agent that reliably closes DRC violations compresses that cycle, shortening the path from RTL freeze to wafer starts.

The tool also deepens the technical coupling between Siemens and TSMC. Foundry-certified flows are the currency of EDA sales; a jointly developed AI fix agent tuned to TSMC's rule decks gives Siemens a differentiated hook with the foundry's customer base, which spans fabless chipmakers designing at every node TSMC offers.

Neither company disclosed pricing, availability dates, or quantitative claims on how much iteration time the agent eliminates. The companies also did not specify which TSMC process nodes the agent supports at launch.

If the agent delivers measurable reductions in sign-off cycles in production use, expect the other major EDA vendors to accelerate their own agentic offerings — and expect foundries to keep pressing for anything that keeps their fabs fed with clean designs.