Siemens and TSMC have extended their EDA collaboration around an AI-powered agent that identifies and fixes design rule violations across digital and custom chip designs, combining Siemens' Calibre, Aprisa and Solido software into an integrated workflow intended to cut the manual labor of verifying that a layout complies with a process's manufacturing rules before tapeout.

The automated workflow forms part of Siemens' Fuse EDA AI System and Fuse EDA AI Agent, engineered to carry out longer, multi-step electronic design automation tasks. According to Siemens, the system coordinates actions across several design tools, assesses intermediate results and verifies its own work as a task progresses. The architecture incorporates NVIDIA AI technologies to improve token efficiency, reasoning and execution for these longer-running workloads.

In design rule checking, Calibre, Aprisa AI and Solido Fuse work in close coordination to identify, analyze and resolve violations. Calibre Check Assist provides contextual guidance and design rule details when engineers investigate problems. The two companies are applying similar agent-based capabilities to custom chip design and physical implementation, where Aprisa supports automated place-and-route — determining how components are arranged on a chip and how their connections are laid out.

The joint deployment concentrates AI automation on defined engineering tasks where the software can check results during execution. In practice, this targets the repetitive design-rule debugging and implementation work that would otherwise demand far more manual intervention.

"AI presents a significant opportunity to drive productivity and efficiency across increasingly complex semiconductor design workflows," said Aveek Sarkar, director of the ecosystem and alliance management division at TSMC. "Our collaboration with OIP partners like Siemens focuses on delivering intelligent, trusted automation that empowers engineers to navigate rising design complexity while achieving stringent performance and energy-efficiency targets. By integrating AI into critical stages of the design process, we enable mutual customers to leverage TSMC's industry-leading processes and advanced packaging technologies to accelerate the expansion of AI innovation."

3D Design and Silicon Photonics

The collaboration extends well beyond flat layout checks. Siemens and TSMC are expanding support for TSMC 3DFabric technologies, which combine multiple dies and packaging technologies within complex designs. Calibre 3DStack Advanced now supports processing across multiple machines for inter-chiplet antenna verification, including designs using TSMC-SoIC wafer-level 3D stacking. Certification work is under way for TSMC's CoWoS-L packaging technology.

The joint efforts also cover thermal analysis, chip-package co-design and routing between separate dies. Calibre 3DThermal has been certified for static and transient thermal analysis of TSMC 3DFabric technologies and the TSMC A16 process, and enablement has been completed for a system-on-wafer thermal reference flow. Siemens and TSMC are also progressing support for 3Dblox, TSMC's framework for 3D chip design, including chip-package co-design workflows. Within that environment, Aprisa is being developed to automatically determine die-to-die routing configurations based on simulation results and signal-integrity requirements.

Silicon photonics adds another dimension through TSMC-COUPE, the Compact Universal Photonic Engine. Siemens tools are already enabled for design, implementation and verification using the technology, with further thermal validation still in progress.

Fresh Certifications on A14

Siemens has secured certifications for several verification tools on TSMC's A14 process: Calibre nmDRC for design rule checking, Calibre nmLVS for comparing a physical layout against its circuit design, Calibre xACT for extracting electrical characteristics and Calibre PERC for electrical reliability checks. The Solido Simulation Suite is certified for SPICE accuracy across TSMC N3C, A16 and A14 technologies, covering analog, radio-frequency and memory verification.

On the power-integrity side, Siemens' mPower software is certified for transistor-level voltage-drop and electromigration analysis on TSMC N2P for digital and analog designs, and on N3C for analog designs. Work continues on N2 and N3 reference flows, while certification of Aprisa and mPower analog software for A14 remains under way.

Siemens has also broadened the technical ecosystem by opening its Xcelerator Academy training program to TSMC Design Center Alliance partners alongside mutual customers. The curriculum includes a digital implementation tutorial based on TSMC's 5 nm process technology.

With agent-based automation now reaching from routine DRC debugging through 3Dblox chip-package co-design, and certifications trailing TSMC's roadmap from N3C to A14, the Siemens-TSMC axis gives foundry customers an increasingly AI-mediated path from RTL to advanced packaging.