Synopsys and OpenAI to teach AI models to use EDA design tools

AI & Compute

Synopsys and OpenAI to Build Specialised Model for EDA Chip Design

Synopsys and OpenAI will jointly develop GPT-Synopsys, a specialised model trained to operate Synopsys EDA tools and run semiconductor design workflows under a revenue sharing deal.

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Nathan Brooks
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Synopsys and OpenAI have agreed to jointly develop GPT-Synopsys, a specialised AI model optimised to operate Synopsys' EDA tools and execute semiconductor design workflows.

The partnership, reported by Electronics Weekly, pairs the industry's largest electronic design automation vendor with the operator of one of the world's most widely used frontier model families. The goal is not a general-purpose language model but one trained and tuned specifically to drive Synopsys' toolchain — the software that engineers use to design, simulate, verify and lay out integrated circuits.

Central to the commercial structure is a revenue sharing arrangement between the two companies. That detail matters: Synopsys is not simply licensing OpenAI technology or buying API access. The two firms will share income generated by the joint model, aligning incentives around a product neither could credibly build alone. OpenAI brings model architecture and training expertise; Synopsys brings proprietary tools, design data domain knowledge and direct relationships with virtually every major chipmaker.

The deal signals a shift in how AI enters the semiconductor design chain. To date, machine learning in EDA has largely meant point optimizations — placement and routing acceleration, lithography hotspot detection, regression triage — embedded inside tools by vendors themselves. An agent-style model capable of operating design workflows end to end would move AI from a feature to an operator, executing multi-step tasks across Synopsys' product families on an engineer's behalf.

For Synopsys, the move is defensive and offensive at once. Its EDA franchise, consolidated further by the recent acquisitions of Ansys and smaller point-tool vendors, generates billions in annual revenue and sits upstream of every advanced-node chip project. If AI agents can meaningfully automate design flows, the first credible implementation inside its own tools protects that position. Competitors Cadence and Siemens EDA are pursuing their own AI strategies, and model providers eyeing the chip design market would find a dedicated EDA-trained model a hard moat to cross.

For OpenAI, the agreement extends a pattern of vertical-specific model development. Chip design is an attractive target: workflow complexity is extreme, tool invocation is highly structured, and the customer base — fabless designers, foundries, IDMs — is concentrated and pays premium software prices.

Details of the arrangement beyond the joint model and revenue sharing — financial terms, development timeline, expected release date, and which Synopsys product lines the model will address first — remain undisclosed.

If GPT-Synopsys reaches production, it could reshape pricing across EDA: value would shift from per-seat tool licenses toward outcomes delivered by AI-operated workflows, a model Synopsys is better positioned to monetize through revenue sharing than through traditional licensing alone. Whether customers trust an AI agent with tapeout-critical flows will decide adoption speed.

Source: Electronics Weekly

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Nathan Brooks

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Senior reporter covering industry trends and analytics at Chip Dispatch.

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