Synopsys Sees AI Agents Reshaping Chip-System Validation

By Tom Whitfield

Synopsys is validating its Autopilot platform and specialized AI agents across more than 50 customer projects. Samsung Electronics, TSMC, Intel, Microsoft and MediaTek are among the participants.

Separately, Synopsys says an autonomous verification workflow developed using Nvidia AI technology expanded verification coverage by 20%. It also reduced the time required to obtain verified RTL by as much as 50 times.

Synopsys frames the change as a new engineering responsibility. Chip designers must become system validators, assessing whether AI-generated results are accurate and safe.

What must chip engineers validate?

The company sees this capability as a key competitive advantage for South Korea, which has expertise in high-bandwidth memory (HBM) and semiconductor packaging. Synopsys expects those strengths to matter more as advanced chips and packages demand broader engineering checks.

Frank Schirrmeister, vice president of strategic programs for system solutions at Synopsys, said in a recent interview:

"As AI adoption drives increasingly sophisticated automation, understanding fundamental engineering principles becomes even more important. Future chip designers will need comprehensive capabilities spanning semiconductor fundamentals, software, electronics and multiphysics analysis, rather than expertise in a single domain."

That mandate makes system validation broader than code review. Engineers must understand how semiconductor behavior, software, electronics and physical effects interact in the finished product.

In plain terms, engineers cannot accept AI output as final evidence that a chip works.

Where does agentic AI stand in chip design?

Synopsys places current AI adoption in semiconductor design at the "orchestrated agents" stage. At this stage, agents divide tasks within a single domain, such as functional verification.

Within functional verification, the agents can handle:

• Specification interpretation
• Register-transfer level, or RTL, generation
• Test planning
• Bug fixing
• Verification completion

The next stage, which Synopsys calls "multi-domain agents," coordinates design, verification and simulation across separate domains. This broader coordination remains a roadmap, not a current end-to-end design capability.

Schirrmeister said:

"Agentic AI-based chip design will spread across individual workflows rather than being introduced all at once, like flipping a switch."

He expects the stage in which AI coordinates the entire engineering process to take shape over the next several years. Productivity gains can arrive earlier as individual workflows improve, but broader coordination requires those tools to work together reliably.

In practical terms, automation will arrive one workflow at a time before it can manage the whole design process.

Why smaller nodes raise the validation burden

At angstrom-scale nodes, Synopsys says power leakage, signal delays, thermal deformation and electromagnetic interference increase exponentially. Transistor scaling alone is becoming insufficient for gains in power, performance and area, the three measures grouped as PPA.

Similar challenges arise in HBM and multi-die packaging. Heat and interference generated by stacking chips or placing them close together can reduce performance and shorten lifespan.

These effects force engineers to validate relationships, not just individual blocks. A design can pass functional checks while its power, heat, electromagnetic interference or package behavior still constrains the final product.

In plain terms, scaling makes validation more cross-disciplinary because physical effects increasingly determine functional performance.

How Synopsys links analysis with EDA

Synopsys combines Ansys' multiphysics analysis technology with its EDA engines to manage these interactions from the earliest stages of development. The approach coordinates design, manufacturing, material-property analysis and packaging work, with the final product as its focus.

The software powering this approach is the Synopsys Autopilot platform. It deploys multiple AI agents for design and verification that can independently reason, plan and execute EDA tools. Autopilot supports both Synopsys' specialized agents and external AI models.

Schirrmeister said companies adopting Autopilot are seeing initial benefits in semiconductor design verification, implementation and PPA optimization. That supports early workflow adoption, but it does not establish a finished end-to-end autonomous design system.

The commercial value lies in linking domain-specific agents to shared multiphysics analysis early, rather than treating design and packaging as separate exercises.

What do the early deployments show?

Fujitsu separately reported a 10% to 30% improvement in RTL code-generation productivity using Synopsys' verification AI agents. The Nvidia-assisted result and the Fujitsu figure are company-reported deployments, not a common industry benchmark.

They nevertheless provide evidence of workflow-level gains in verification, implementation, PPA optimization and code generation. Synopsys expects those benefits to develop further as specialized agents gain the ability to coordinate across engineering domains.

Over the next several years, Synopsys expects agentic functions to spread across individual workflows while coordination of the whole engineering process takes shape. The commercial test is whether today's verification and coding gains can scale, particularly for South Korea's HBM and packaging base, without losing accuracy or safety.