Thousands of IP Blocks, Nowhere to Track Them: SoC Integration Pain Grows

A design that carried tens of IP blocks a decade ago may now carry thousands, with dozens of versions of the same block — and, according to Pedro Pires, SOS product manager at Keysight EDA, "it is becoming very difficult to manage in an ad hoc way." That arithmetic, more than any single bug class, explains why IP integration remains one of semiconductor engineering's most persistent trouble spots nearly three decades after the industry first tried to standardize it.

The Virtual Socket Interface Alliance (VSIA) formed in 1996 to unify how IP was built, verified, delivered and supported. It dissolved in 2008, judging its work complete or handing pieces to narrower organizations. Eighteen years on, the problem has only evolved — grown, really — as chipmakers lean on third-party blocks to focus their own effort on what is genuinely novel.

Where do the nastiest bugs live?

Between blocks, not inside them. "The nastiest failures are almost never inside a single block," says Ashish Darbari, founder and CEO of Axiomise. "They show up between blocks — message-dependent deadlock, credits that slowly leak away, a reorder buffer that gets corrupted, an ordering rule broken across a bridge. Each block passes its own verification, yet the system hangs because two teams read the same protocol rule slightly differently."

Synopsys' Madhumita Sanyal, senior director for technical product management for the HPC IP portfolio, ticks through the cross-IP fault surface: address mapping, interrupts, coherency, QoS, security, DVFS power schemes, and OS interaction. Add die-to-die IP and the list grows to known-good-die packaging, signal and power integrity, thermal coupling and telemetry.

Size alone isn't the measure. "I may be designing a giant CPU with 32 cores, but that is just 32 copies of the same thing," says IC Manage CEO Dean Drako. "The complexity is not always proportional to the size of the chip... The human brain can't deal with it." What matters is assumptions. A UART needs a clock, a reset and a register interface, Darbari notes. A CHI home node or a NoC carries hundreds — ordering rules, credit contracts, transaction limits, reset sequencing, address maps, security attributes.

Why do specifications keep failing?

Because nobody writes down what the system as a whole must do. "The architect, the designer, the software team, the DV lead and the formal team all look at the same failure and see something different," says Darbari. Those disagreements exist from day one but surface two years later, often in post-silicon debug, when fixes cost most. Keysight's Pires adds that IP documentation frequently lacks the information to predict behavior under all operating conditions.

Software deepens the hole. Even a simple PHY ships boot firmware, calibration firmware, OS interrupt and DMA framework dependencies, and BIOS or hypervisor entanglements, Sanyal says. UCIe 3.0 standardizes how firmware loads early in initialization, but hardware is often only correct under software assumptions — register programming order, fields that must never be written mid-transaction — that "RTL verification on its own never checks," per Darbari.

What about power, analog and chiplets?

"Power management has become a functional feature, and a major source of functional bugs," says Darbari. A block can be correct while powered on yet drop a transaction when a neighbor powers down mid-transfer. Chris Morrison, VP of product marketing at Agile Analog, says analog IP must now actively manage the chip through embedded PVT sensors, timing monitors, droop and glitch detectors feeding real-time telemetry to power management units. Customers increasingly want complete analog subsystems wrapped digitally, with SystemVerilog real-number models enabling full-chip verification in a digital environment.

Chiplets turn IP integration into supply chain integration, says Synopsys' Frank Schirrmeister — dies from different companies, nodes and foundries, each with its own verification methodology. NoCs now stretch across die boundaries, and a chiplet looks less like a passive block and more like a small system with its own management firmware, Darbari notes. Encrypted delivery compounds the verification problem: vendors verified some configuration set, but tapeout likely uses one nobody tested.

Version control is its own mess. Hardware and software versions are often linked only in "messy and error-prone" Excel spreadsheets, Pires says, and field firmware updates can change silicon behavior after signoff.

Still, EDA's pattern holds: as a problem grows, so does investment. "In relative terms, the pain remains constant, but the problem underlying it is a bigger one," says Pires. A second part of the report will cover how AI is being applied to IP selection, configuration and integration.