TSMC's chief executive has told investors that the company's profitability has no ceiling, and confirmed the foundry plans to adopt High-NA EUV lithography in 2030, according to a DigiTimes report.

Two claims, one message. CEO C.C. Wei framed the remarks as a statement of confidence in TSMC's pricing power and its grip on the leading edge, where the foundry remains the sole high-volume supplier of the industry's most advanced logic.

The 2030 date matters. Rival Intel has already taken delivery of ASML's High-NA Twinscan EXE:5000 tools and is running them in development. TSMC, by contrast, has said repeatedly it can extend today's standard EUV — the NXE platform with 0.33 numerical aperture — using multipatterning before it needs High-NA's 0.55 NA optics. A 2030 adoption target puts High-NA insertion several node generations out, likely beyond the N2 and A16 era and into the roadmap's later entries.

That timing is a commercial decision as much as a technical one. Each High-NA scanner costs roughly $380 million, and early adopters absorb the yield-learning burden. Waiting until 2030 lets TSMC ride a larger installed base of mature, depreciated EUV tools while rivals burn capital on first-generation High-NA systems.

What does 'no ceiling' on profitability actually mean?

Wei's phrasing is aggressive even by foundry standards. TSMC has posted gross margins above 50% in recent quarters, and management has defended those margins through price increases negotiated with customers across successive nodes. Saying profitability has "no ceiling" signals the company expects to keep raising prices on leading-edge capacity — and expects customers, from Apple to Nvidia to AMD, to keep paying.

The leverage comes from concentration. Most of the world's most advanced chips fab at TSMC in Taiwan, and no competitor matches its combination of yield, capacity and node cadence. Samsung Foundry continues to chase; Intel Foundry is building out its contract business under new leadership. Neither has yet eroded TSMC's share at the bleeding edge.

Why the High-NA date changes the tool market

For ASML, a 2030 commitment from TSMC sets the volume clock for High-NA shipments. The Dutch lithography maker has shipped only a handful of EXE systems so far, all to development programs. A production insertion by the world's largest foundry in 2030 implies meaningful High-NA order volume late this decade — revenue ASML can bank on top of the ongoing standard-EUW backlog.

For TSMC's equipment peers — Applied Materials, Lam Research, KLA, Tokyo Electron — the date is a neutral-to-positive marker. Node transitions pull fresh deposition, etch and metrology spend regardless of which scanner prints the wafers.

Geopolitics sits quietly behind all of this. High-NA EUV tools remain export-restricted to China, which sharpens TSMC's edge over any would-be SMIC-led challenger at the leading edge and reinforces why leading-edge capacity in Taiwan, Arizona and Japan carries strategic premiums.

The road to 2030

Between now and then, TSMC must execute. N2 enters volume production this year using nanosheet transistors, followed by A16 with backside power delivery. Each step raises capex — the company guided roughly $38–42 billion for 2025 — and each step tests whether margins hold as costs climb.

Wei's bet is that pricing power outruns cost. If customers keep queuing for leading-edge wafers, and High-NA arrives in 2030 only after standard EUV is fully milked, the margin ceiling stays uncapped — at least until a rival proves it can compete at the same node, on the same scale, at the same time.