TSMC’s A16 process targets volume production in 2027

By Grace Kim

TSMC targets A16 volume production in 2027, about one year before Intel’s planned 14A ramp.

TSMC expects its A16 process to reach production readiness in 2026. Customer product ramps point to volume production in 2027. The 1.6-nanometer-class node targets high-performance computing products with complex signal routing and dense power-delivery networks.

What performance gains does A16 promise?

TSMC says A16 improves on its N2P process in three stated ways.

• Performance: 8% to 10% faster at the same power draw.
• Power: 15% to 20% less power at the same speed.
• Density: roughly 8% to 10% higher transistor density.

For chips that run hot around the clock, including AI accelerators, claimed power savings can translate into more efficient sustained operation inside crowded data-center systems. The figures are TSMC’s own comparisons with N2P.

A16 also marks TSMC’s first use of Super Power Rail. The architecture moves the power-delivery network to the back of the wafer rather than routing it alongside signal wires on the front. TSMC designed the change for dense, power-hungry computing products.

Why is TSMC not using High-NA EUV?

TSMC is developing A16 without ASML’s High-NA EUV lithography systems. Each tool costs north of €350 million. At an earlier briefing on the node, Zhang said: “I like the technology but I don’t like the sticker price.”

TSMC says it is squeezing A16’s gains from its existing EUV fleet and process engineering. The approach does not require a High-NA purchase while keeping A16 on its stated schedule. It also makes process engineering, rather than tool ownership, the immediate route to higher performance and lower power.

By contrast, Intel became the first chipmaker to receive ASML’s High-NA system and plans to use that equipment for production of its competing 14A process. Intel’s equipment choice does not settle the commercial race. A costly tool only pays off if the competing node ships on time. At present, TSMC’s A16 route sits closer to volume production without that machine.

How do Intel and Samsung roadmaps compare?

Intel CEO Lip-Bu Tan said this year that the company has fully committed to high-volume 14A production in 2028. Intel plans risk production for internal chips in the second half of 2027. The commitment accelerates Intel’s position from one year earlier, when it warned it might abandon 14A without a major external customer.

Samsung’s SF1.4 node does not target mass production until 2029. That is two years later than the production target Samsung announced in 2022.

On current roadmaps, A16 could enter volume production roughly one year ahead of Intel’s 14A ramp and two years ahead of Samsung’s SF1.4 target schedule. These dates remain targets rather than confirmed volume shipments.

What has Intel already shown with High-NA EUV?

Intel Foundry has shipped the first high-volume logic chips built with ASML’s next-generation High-NA EUV lithography, years ahead of TSMC’s own timeline. The milestone lands on Intel’s Core Ultra Series 3 Panther Lake chips, built on the 18A node. Reported yields match those from older EUV tooling.

That is a real technical win. Its commercial value still depends on converting the manufacturing result into competitive production at the required scale.

Intel’s 18A achievement demonstrates manufacturing reach, but the separate 14A schedule must still deliver high-volume production on the company’s stated 2028 timetable without schedule slippage.

Who is driving leading-edge demand?

Every hyperscaler is racing to stand up the next generation of AI data centers. Nvidia, AMD, and the custom-silicon teams at Amazon, Google, and Microsoft are among the organizations seeking leading-edge capacity for next-generation accelerators. Whoever prints those chips first can set the pace for the broader AI hardware buildout.

Leading-edge capacity now links process timing to accelerator launches, data-center construction schedules and the pace of the wider AI hardware buildout across chipmakers and cloud operators.

Wall Street has spent much of 2026 debating whether AI spending is a bubble about to pop. The production calendar does not depend on that argument.

What does the capacity book show?

Supply-chain reporting indicates that much of TSMC’s initial N2 capacity has been heavily booked. TSMC says it plans to more than double annual N2-family capacity in 2027 to meet strong smartphone and high-performance-computing demand. The bookings show pricing power in TSMC’s order book. The capacity target is a plan, not a disclosed wafer-volume figure.

For founders and product teams building downstream custom silicon, ranging from AI inference chips to next-generation networking gear, the practical constraint is access to advanced foundry capacity. The critical path runs through TSMC’s fabs in Taiwan.

If A16 follows its stated schedule, TSMC could gain pricing power with designers who value leading-edge performance, power efficiency and earlier accelerator deployment windows together. If TSMC delivers A16 and its N2 expansion on schedule, it can reinforce pricing power before Intel and Samsung narrow the schedule gap.